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Available on both 45nm and 65nm process technology, these quad-, dual- and single-core Intel® Xeon® processor-based platforms feature outstanding performance, energy efficiency and extended lifecycle support. They are ideal for compute-intensive embedded, storage and communications applications including storage area networks, network attached storage, routers, IP-PBX, converged/unified communications platforms, sophisticated content firewalls, unified threat management systems, medical imaging, military signal and image processing and telecommunications (wireless and wireline) servers.
Intel® Core™ microarchitecture supports improved performance on multiple application types and user environments as well as performance/watt. Platform power savings is derived from lower TDP in the MCH, the efficient next-generation Intel® I/O Controller Hub 9R and standard native DDR2 memory technology, with a maximum capacity of 48 GB. 1066/1333 MHz FSB speeds data transfer for increased throughput.
Intel® 82576 Gigabit Ethernet Controller Product Brief
Version: 001 : June 2008
Intel® 82599 10 Gigabit Ethernet Controller Product Brief
Version: 001 : March 2009
This product brief provides an overview of the features, benefits and configurations for Quad-Core and Dual-Core Intel® Xeon® processors.
Version: 004 : September 2008
Δ Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number/ for details.
‡ L3014 is a single-core Xeon processor.
This document discusses the design of an open, modular, scalable system for the delivery of converged communications.
Version: 001 : January 2009
This application note explains how to use the CPUID instruction in software applications, BIOS implementations and processor tools.
Version: 036 : August 2009
This document provides a context for using the features for manufacturability and debug implemented on Intel® processors and chipsets.
Version: 001 : October 2007
This manual provides information about programming SPI flash on ICH family based platforms.
File Type/Size: PDF 929KB
Version: 2.4 : September 2008
This brief helps users understand how to implement Serial Peripheral Interface Flash and its uses in applications.
File Type/Size: PDF 280KB
Version: 1.0 : June 2008
This white paper examines new innovations that improve the performance and energy efficiency of Intel® architecture, including instructions on SSE4 and application targeted accelerators.
Version: 001 : September 2006
Intel® Socket Test Technology for LGA771 has been developed to provide solder-joint and pin contact coverage for LGA771 sockets that have been assembled onto motherboards.
Version: 001 : February 2006
An increase in the speed and frequency of a design combined with a need to reduce cost has created a challenge in defining an acceptable stack-up to meet the needs of high-speed designs.
Version: December 2008
This paper discusses the software methods used to access PCI Express* registers, including the formula used to calculate the memory locations needed to access a specific register.
This paper covers what it takes to set up the IA-32 architecture and potential usage models for asymmetric multiprocessing.
Version: January 2009
This paper examines storage solutions, from USB flash drives to high capacity disk drives, and discusses the trade-offs in finding the right solutions for an embedded application.
As this white paper shows, embedded system developers may find added performance for particular workloads when hardware and software prefetching is finely tuned.
DDR is one of the challenging interfaces for a signal integrity engineer. This paper outlines an approach to divide the task, with an example for each step from the DDR2 interface.
Here are recommendations for engineers who are designing embedded systems with the minimum number of power rails, including power and reset sequencing for standby and main rails.
This paper provides insights on how high speed signals behave on a board, the role played by inductors, resistors and capacitors and available design tools.
Since memory latency is an important factor of overall performance, it is important to know what tool to use in order to gather this information.
I²C bus protocols can differ slightly from Intel® Controller Hub (ICH) SMBus protocols.This paper provides a full description of the details of each SMBus cycle supported by the ICH.
Description of Intel® Core microarchitecture.
Version: 002
Information on the NEXUS automotive JTAG, the Intel XDP and ITP and available debuggers.
This paper explores design paradigms for data plane packet processing on multi-core Intel architecture systems and their impact on data structure design and synchronization primitives.
MSI delivery and servicing removes the two big limitations associated with Intel® architecture, the limited number of interrupts and unnecessarily high interrupt latencies.
Based on real-world applications, these tips will help programmers migrating to multi-core systems avoid some of the pitfalls that can come with the new parallel paradigm.
Intel delivers platform design guidelines with validated platforms. This document details the signal integrity impacts from every deviation and describes solutions to overcome them.
This document provides guidance to thermal engineers and system designers regarding thermal concerns including volumetric constraints, environmental boundary conditions and power limits.
This paper uses PiAutoSim*, a bench-top simulator, to show how upgrading the hardware and software development environment of an embedded product enables significant performance improvements.
This white paper examines multi-threading opportunities in embedded applications using Intel® software products, and includes an analysis of the Open-iSCSI storage application.
Version: 001 : April 2008
Ensuring sufficient hardware level I/O capabilities for embedded designs is critical. This paper outlines the PCIe hardware level benchmarking used by Intel to collect I/O performance data.
L3 forwarding measures the Intel® architecture core capability in processing IP packets without any loss. This paper explains L3 forwarding measurement and optimization techniques.
This paper explains the four elements of architectural trade-offs made by system architects, including performance characteristics of these configurations and tuning recommendations.
File Type/Size: PDF 455KB
This provides developers a better understanding of the PCI Express* performance capabilities of the Intel® 5100 Memory Controller Hub for designing embedded solutions with IO usage models.
File Type/Size: PDF 301KB
This paper discusses the L3 forwarding performance for Quad-Core Intel® Xeon® Processor L5410 with Intel® 5100 MCH platform.
File Type/Size: PDF 332KB
Essential information about third-party clock chips used in Intel platforms.
File Type/Size: PDF 2,813KB
Version: 1.0
This datasheet contains complete register, signal and system address map information as well as electrical characteristics, functional descriptions and testability.
Version: 005 : July 2009
Intel® 82576 Gigabit Ethernet Controller Datasheet
Version: 2.41 : April 2009
Intel® 82599 10 Gigabit Ethernet Controller Datasheet
Version: 2.01 : July 2009
Datasheet for the Intel® 82801IB ICH9, 82801IR ICH9R, 82801IH ICH9DH, 82801IO ICH9DO, 82801IBM ICH9M and 82801IEM ICH9M-E, and ICH9M-SFF ICH9-I/O controller hubs.
Version: 004 : August 2008
The Quad-Core Intel® Xeon® Processor 5400 Series Datasheet provides technical design information for hardware/software/design engineers.
Version: 005 : August 2008
Essential information about third-party clock buffers used in Intel platforms.
File Type/Size: PDF 388KB
Version: 2.0
This document includes electrical, mechanical and thermal specifications, including electrical, signal quality and package mechanical specifications.
File Type/Size: PDF 4,859KB
Version: 2.3 : July 2007
This is the main processor component specification document, including electrical, mechanical and thermal specifications.
File Type/Size: PDF 3,565KB
Version: 2.2 : August 2008
Revision to the External Design Specification for the Intel® 5100 Memory Controller Hub (MCH) Chipset.
File Type/Size: PDF 4,601KB
Version: 2.2 : July 2008
Addendum to the External Design Specification for the Intel® 5100 Memory Controller Hub (MCH) Chipset.
File Type/Size: PDF 438KB
Essential information on the Intel® 82801Ix I/O Controller Hub, including signal register and functional descriptions, as well as electrical and package characteristics.
File Type/Size: PDF 6,952KB
Version: 2.3 : June 2008
Intel® Xeon® Processor 5300 Series Boundary Scan Description Language (BSDL) model.
Version: 003 : September 2007
This document updates several documents and is a compilation of device and documentation errata, specification changes and specification clarifications.
Version: 017 : June 2009
This document updates several parent and related documents, and provides a compilation of errata, specification changes, specification clarifications and document-only changes.
Version: 008 : August 2009
Intel® 82576 Gigabit Ethernet Controller Specification Update
Version: 2.3 : May 2009
Intel® 82599 10 Gigabit Ethernet Controller Specification Update
Version: 2.0 : August 2009
This is a flash utility that is supplied with the BIOS that can be used to program the firmware hub (FWH).
File Type/Size: PDF 169KB
Version: 2.0 : November 2008
This document contains revised information about Intel 82801Ix products including identification information, specification changes and clarifications, documentation changes and errata.
File Type/Size: PDF 247KB
Version: 1.0/Rev013 : November 2008
Intel® I/O Controller Hub 9 (ICH9) Family Specification Update.
Version: 018 : August 2009
This document is a compilation of errata, specification clarifications and changes for the Intel® Xeon® Processor 5100 Series.
Version: February 2008
Version: June 2009
This document compiles errata and specification changes and characteristics regarding the Quad-Core Intel® Xeon® Processor 5300 Series.
This document provides functional, quality, reliability and material requirements and design guidelines for the 603-pin socket used with the Intel® Xeon® processor.
Version: 1.0 : May 2001
This guide provides debugging guidance for Intel® 5000 Series Chipset Based Platforms.
File Type/Size: PDF 284KB
Version: 1.3 : December 2006
The platform design guide provides information for board design, including layout and routing guidelines and platform design details relating to system memory and system power delivery.
File Type/Size: PDF 5,117KB
ITP700 Debug Port Design Guidelines
Version: 1.65 : February 2004
LGA771 Socket Mechanical Design Guide
Version: 002 : November 2006
This document provides design guidance for the VRM 9.0 DC-DC Converter.
Version: 004 : April 2002
This document provides design guidance for the VRM and Voltage Regulator-Down (EVRD).
Version: 002 : July 2005
This document defines the electrical, thermal and mechanical design specifications for Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0.
Version: 002 : April 2008
Intel® 5100 Memory Controller Hub (MCH) Chipset Electronic Pin List and Ballmap for A0 Stepping
File Type/Size: Microsoft* Excel 732KB
Version: 1.2 : May 2007
Intel® 5100 Memory Controller Hub (MCH) Chipset Electronic Pin List and Ballmap for B0 Stepping
File Type/Size: Microsoft* Excel 740KB
Intel® 5100 MCH Chipset Trace Length Calculator (TLC)
File Type/Size: Microsoft* Excel 1,380KB
Version: 2.1 : February 2008
The embedded and communications design guide is focused on helping customers develop solutions for specific market segments.
File Type/Size: PDF 460KB
Version: 1.0 : April 2007
Get your software up and running using boards and development kits from Intel and third-party vendors.
Gold BIOS for Bitan 2—Customer Reference Board (CRB). Bitan is the code name for the 1st revision CRB. The Gold BIOS is validated to work with the Bitan CRB and is available for free.
File Type/Size: ZIP 1,005KB
Version: S08.0 : January 2008
These manuals describe the architecture and programming environment of Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.
A BIOS image is provided to re-install the existing BIOS or install a new version of the BIOS on a platform.
File Type/Size: ZIP 470KB
Version: 1.3 : June 2008
Programmable Logic Device (PLD) reference source code used on the customer reference board provides customers with a reference to port into their own system PLD implementation.
File Type/Size: ZIP 56KB
Version: 1.2
This user guide is designed for developers using the Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset.
A BIOS image is provided to re-install the existing BIOS or install a new version of the BIOS. This is the firmware hub (FWH) image only and is not intended to be used to program the SPI.
File Type/Size: ZIP 469KB
A BIOS image is provided to re-install the existing BIOS or install a new version of the BIOS. This is the SPI image only and is not intended to be used to program the firmware hub (FWH).
File Type/Size: ZIP 471KB
Purchase Intel® embedded products from Intel® Authorized Industrial Distributors.
If you already have an account set up with Intel, contact your CBA for order placement. If you are not currently set up with Intel, visit the “Where to Buy” section of the EDC.
Intel® 82576 Gigabit Ethernet Controller Driver Download
Intel® 82576 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.
File Type/Size: ZIP 7KB
The 82599 Silicon Sample Kit is a zip file containing basic product information and tools that enable a customer to bring up a Silicon product sample during their validation or evaluation of the sample.
Intel® 82599 10 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.
Version: 1.3 : June 2009
This video outlines a high-performance, energy-efficient platform targeted at bladed and dense-bladed that are required to fit within a 200-watt power envelope. Duration: 2:24.
This document provides an overview of the Intel® 5100 Memory Controller Hub Chipset for communications, embedded and storage applications.
File Type/Size: PDF 2,325KB
The presentation contains information for design engineers designing systems using this Intel® 5100 Memory Controller Hub Chipset-based platform.
File Type/Size: PDF 3,123KB
Product specific and customer action information that includes features/benefits, functionality, launch information, inventory updates and marketing presentations.
File Type/Size: PDF 1,740KB
Version: April 2008
Overview of the Quad-Core and Dual-Core Intel® Xeon® Processor 5000 Sequence with Intel® 5100 Memory Controller Hub Chipset.
File Type/Size: PDF 743KB
Version: 3.1 : April 2008
Product brief for the Intel® Xeon® 5400, 5300, 5200, 5100 and 3000 series platform for embedded and communications applications.
Version: 004 : January 2008
Customer Reference Board (CRB) schematics and layout for the Bitan CRB. These CRB files can help developers start designing an 8-layer PCB including the Cranberry Lake platform.
File Type/Size: ZIP 8,629KB
File Type/Size: ZIP 9,508KB
Version: 1.0 : August 2007
File Type/Size: ZIP 9,729KB
Version: 1.0 : September 2007
Contains Cadence* Concept* symbols for Intel® 5100 Memory Controller Hub Chipset, ICH9R and supported processors.
File Type/Size: ZIP 156KB
Contains Cadence* OrCAD* symbols for the Intel® 5100 Memory Controller Hub Chipset, ICH9R,and supported processors.
File Type/Size: ZIP 45KB
Version: 1.3 : January 2008
Contains preliminary pre-silicon CRB design layout placement data, schematics and BOM for the Intel® 5100 Memory Controller Hub Chipset.
File Type/Size: ZIP 18,825KB
Version: 1.3 : August 2007
Contains CRB design layout placement data, schematics and BOM for the Quad-Core and Dual-Core Intel® Xeon® Processor 5000 Sequence with Intel® 5100 Memory Controller Hub Chipset.
File Type/Size: ZIP 18,479KB
Version: 2.1 : March 2008
The input/output (I/O) buffer information specification model defines a buffer's characteristics for all of the I/O pins of the device.
File Type/Size: ZIP 739KB
Version: 2.1 : April 2008
File Revision for the Intel® 5100 Memory Controller Hub (MCH) Chipset A0 Stepping Boundary Scan Description Language (BSDL).
File Type/Size: ZIP 117KB
File Type/Size: ZIP 25KB
Version: 2.2
File Type/Size: ZIP 5,585KB
Version: 1.6 : June 2007
Contains BSDL filesthat define the series scan chain for the Dual-Core Intel® Xeon® Processor 5100 Series.
Version: 003 : August 2007
Contains Boundary Scan Description Language (BSDL) files that define the series scan chain for the Dual-Core Intel® Xeon® Processor 5200 Series.
Contains Boundary Scan Description Language (BSDL) filesthat define the series scan chain for the Quad-Core Intel® Xeon® Processor 5400 Series.
Intel® 5100 MCH Chipset Package Thermal Models
File Type/Size: ZIP 18KB
Intel® 5100 MCH Chipset RDIMM Thermal Design Power (TDP) Calculator
File Type/Size: - 86KB
Linux Maximum Power Application for the Intel® 5100 Memory Controller Hub Chipset
File Type/Size: ZIP 170KB
Intel® 5100 Memory Controller Hub Chipset Thermal/Mechanical Design Guide
Version: 003 : July 2008
Software for measuring the maximum power/thermal characteristics of the Quad-Core Intel® Xeon® Processor 5100 Series.
File Type/Size: ZIP 221KB
Version: 1.0.1 : August 2007
This zip file contains the ICH9 component Flotherm* model software file and its corresponding user's guide.
Version: 0.2
This mechanical model is a Pro-E and IGES design file for the optimized Intel® ICH9 platform, and includes all critical functional dimensions of the heatsink and chipset/processor.
File Type/Size: ZIP 402KB
Version: 1.0 : March 2006
This guide contains system and processor thermal design considerations and recommendations and outlines the operating limits for the Intel ICH9.
File Type/Size: PDF 847KB
Version: 1.5
Use this tool to model the mechanical characteristics of the Intel® Xeon® Processor 5000 Series.
Use this tool to model the thermal characteristics of the Intel® Xeon® Processor 5000 Series.
Version: 2.0 : August 2006
This document discusses thermal management and measurement techniques, as well as the impact of integrated thermal management logic.
Version: 001 : June 2006
This document provides an understanding of the processor thermal characteristics and design parameters for the Dual-Core Intel® Xeon® Processor 5200 Series in embedded applications.
Version: 002 : September 2008
This document describes the reference thermal solution and design parameters for the Dual-Core Intel® Xeon® Processor Series.
Version: 001 : November 2007
This document provides an understanding of the processor thermal characteristics and design parameters for the Quad-Core Intel® Xeon® Processor L5408 in embedded applications.
Intel's power profiling kit can accurately measure a platform's total AC, DC and component level power consumption while running standard applications or benchmarks.
Software for measuring the maximum power/thermal characteristics of the Quad-Core Intel® Xeon® Processor 5400 Series.
File Type/Size: application/zip 1,136KB
Version: 1.0 : June 2007
File Type/Size: application/x-gzip 441KB
Version: 1.0.1 : July 2007
This guide describes the reference thermal solution and design parameters for the Quad-Core Intel® Xeon® Processor L5408 in embedded applications.
This document defines thermal cooling: passive, active and fanless thermal solutions and their difference via the three modes of heat transfer—conduction, convection and radiation.
Intel® Embedded Graphics Drivers (IEGD) are a suite of multi-platform graphics drivers designed to meet the requirements of embedded applications.
Intel provides development drivers for Intel® Integrated Graphics to the open source community.
Version: November 2008
Read and accept the software agreement to download source code from N.A. Software. AltiVec* SIMD macros translator software is provided ‘as is.' Intel does not provide support. Please contact N.A. Software for support.
This paper explores technical issues around building, debugging and deploying embedded firmware on an Intel® architecture system.
Presentation introduces N.A. Software AltiVec* SIMD macros translator software. Software is provided ‘as is.’ Intel does not provide support.
File Type/Size: PDF 865KB
Version: April 2009
Information and demos on the Intel® Compiler, Intel® VTune™ Performance Analyzer, Intel® Thread Checker and Intel® Thread Profiler.
OpenMP* is a set of pragmas, function calls and environment variables that simplify the creation, synchronization and deletion of threads in your applications.
Version: September 2007
AMIBIOS8* is a well supported and stable BIOS product adopted by all computing market segments.
The boot security application establishes trust between platform hardware and the user application, preventing the operation of systems compromised by unauthorized tampering.
Embedded BIOS* with StrongFrame* Technology is the sixth evolution of General Software's firmware SDK solution for Intel® architecture designs.
General Software* Embedded UEFI Core with StrongFrame* Technology is UEFI 2.1-specification compliant, giving customers the latest proven EFI technology commercially available.
The Firmbase* SDK is a software development kit that provides customers with the ability to embed General Software's Firmbase Technology into application software.
General Software* High Availability (HA) Monitor* enables embedded systems to autonomously detect and correct including OS crashes, degraded hardware performance and failing hardware.
The platform update facility is firmware that allows manual replacement of disk partitions, files within partitions, CMOS contents and flash memory at any time during its operation.
This site includes downloads for all supported operating systems.
Version: 8.6.0.1006
This paper explains how I/O address aliasing works with respect to these registers for all ICH modes and provides exact programming instructions and sample code.
Browse dozens of technical white papers on Intel® Compilers, the Intel® VTune™ Analyzer, Intel® Performance Libraries, Threading Analysis Tools, Cluster Tools, and XML products.
This presentation from QNX covers Intel's breadth of multi-core solutions and discusses issues developers face when moving to multi-core, with examples.
File Type/Size: PDF 1,534KB
Version: 4 : February 2009
Testing the real-time clock for accuracy under test conditions.
Version: 008 : October 2007
The customer readiness test plan (CRTP) assists in testing and validating chipset-based platforms.
File Type/Size: PDF 2,339KB
Version: 2.1
Run Control Tool EMC XDP
The Intel® 82576 Gigabit Ethernet Controller provides high performance dual-port gigabit connectivity in a multi-core platform, as well as in a virtualized platform. In a multi-core platform it supports technologies including Intel® QuickData Technology, MSI-X, and Low Latency Interrupts that help accelerate the movement of data across the platform, improving application response times. In a virtualized environment, it supports Intel® Virtualization Technology for Connectivity that helps improve I/O performance by reducing I/O overhead.
The Intel® 82599 10 Gigabit Ethernet controller and Intel® Xeon® processor 5500Δ series-based servers deliver unmatched performance scalability in the data center. The Intel 82599 10 gigabit Ethernet controller includes Intel® Virtualization Technology for Connectivity (Intel VT-c) to deliver outstanding performance in virtualized server environments. The controller reduces cost and complexity of the data center by combining LAN and SAN traffic onto a single Ethernet fabric. Customers can use iSCSI, NAS or FCoE to carry storage traffic over Ethernet. In order to meet SAN requirements for guaranteed packet delivery, the controller implements capabilities including enhanced transmission selection and priority flow control. This controller is deal for embedded applications in telecommunications infrastructure, industrial, medical, military, interactive client, infotainment, and print imaging applications.
Videos, online classes & eLearning by Mindshare*.
Terms for embedded developers with definitions from Intel.
Intel® Embedded Alliance is a trusted supply line of Intel-based products and services where member companies offer solutions to speed development, design and reduce costs.