Intel® Embedded Design Center

+ Specifications

Based on the latest generation Intel® microarchitecture (codenamed Nehalem), the Intel® Xeon® processor 5500 series is designed for high performance in bandwidth-intensive applications including communications and storage. The processors include Intel® Virtualization Technology¹ for flexible virtualization and represent the next step in energy-efficient performance with an integrated memory controller. This platform is an excellent choice for thermally constrained and bladed applications.

Based on 45nm process technology, processors in the Intel Xeon processor 5500 series are available in quad-core and dual-core options with thermal design power (TDP) from 80W to 38W. The two processor options are suitable for AdvancedTCA* blades and enable compliance with NEBS level-3 thermal specifications. The processors can be used in single or dual-socket configurations with the Intel® 5520 chipset, consisting of the Intel® 5520 I/O Hub and Intel® I/O Controller Hub ICH10R, which supports up to 42 PCI Express* lanes, SATA ports and RAID.

¹ Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

+ Platform highlights

Low-power and robust thermal profile processor options are ideal for NEBS level-3 ambient thermal specifications and smaller form factors with thermal constraints.
Automated low power states put processor, memory and I/O controller into the lowest available power states while meeting requirements of the current workload.
Up to 144 GB of main memory supports high performance for data-intensive applications.
Integrated memory controller reduces memory latency.
Intel® Virtualization Technology for Directed I/O helps speed data movement by giving designated virtual machines their own dedicated I/O devices, reducing performance overhead.

Mouse over Intel components to learn more

Intel® I/O Controller

Intel® 5520 Chipset

Intel® 82576 GbE Controller
Intel® 82599 10 GbE Controller
Product Brief: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Product Brief

Version: 001 : June 2008
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Product Brief

Version: 001 : March 2009

Intel® Xeon® processor E5504
Intel® Xeon® processor E5540
Intel® Xeon® processor L5508
Intel® Xeon® processor L5518
Product Brief: Intel® Xeon® 5500 Platform for Embedded Computing

Product brief for the Intel® Xeon® 5500 Platform for Embedded Computing.

Version: 002 : April 2009

Intel® Xeon® Processor 5500 Series for Embedded Computing

Processor Number	Intel® Xeon® processor E5540Δ
CPU Frequency	2.53 GHz
Turbo Boost Technology¹	Yes
Intel® Hyper-Threading Technology²	Yes
L3 Cache	8 MB
Number of Cores	4
Power	80W
Robust Thermal Profile (High Tcase)	Standard
Intel® QuickPath Link Speed‡	5.86 GT/s
DDR3 Memory	1066/800

Processor Number	Intel® Xeon® processor E5504Δ
CPU Frequency	2.00 GHz
Turbo Boost Technology¹	No
Intel® Hyper-Threading Technology²	No
L3 Cache	4 MB
Number of Cores	4
Power	80W
Robust Thermal Profile (High Tcase)	Standard
Intel® QuickPath Link Speed‡	4.8 GT/s
DDR3 Memory	800

Processor Number	Intel® Xeon® processor L5518Δ
CPU Frequency	2.13 GHz
Turbo Boost Technology¹	Yes
Intel® Hyper-Threading Technology²	Yes
L3 Cache	8 MB
Number of Cores	4
Power	60W
Robust Thermal Profile (High Tcase)	85° C³
Intel® QuickPath Link Speed‡	5.86 GT/s
DDR3 Memory	1066/800

Processor Number	Intel® Xeon® processor L5508Δ
CPU Frequency	2.00 GHz
Turbo Boost Technology¹	Yes
Intel® Hyper-Threading Technology²	Yes
L3 Cache	8 MB
Number of Cores	2
Power	38W
Robust Thermal Profile (High Tcase)	85° C³
Intel® QuickPath Link Speed‡	5.86 GT/s
DDR3 Memory	1066/800

Intel® 5520 Chipset for Embedded Computing
Product	Package	Features
Intel® 5520 I/O Hub (36D)	FCBGA1295	Supports Intel® Xeon® processor 5500 series at 6.4 GT/s, 5.86 GT/s and 4.8 GT/s speeds via Intel® QuickPath Technology interconnect. Supports 36 lanes of PCI Express* 2.0 I/O, Intel® VT-c and Intel® VT-d enhancements for virtualization OS, and Intel® ICH10R; 27.1W TDP. Optional second Intel® 5520 IOH supports up to 72 lanes PCI Express* 2.0.
Intel® I/O Controller Hub (ICH10R)	PBGA676	PCI Express* 6x1; six SATA ports; Intel® Matrix Storage Technology with RAID 0, 1, 5 and 10; 12 USB ports, Integrated Gigabit LAN controller 10/100/1000; 4.5W TDP.

Δ Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor series, not across different processor sequences. See www.intel.com/products/processor_number/ for details.

¹ Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost.

² Hyper-Threading Technology requires a computer system with a processor supporting Hyper-Threading Technology and an HT Technology-enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm

³ Not to exceed 360 hours per year.

‡ GT/s = giga-transfers/second

Application notes
Benchmarks
Datasheets and specification updates
Design calculators, checklists and guides
Development boards and kits
Ethernet controllers

Platform overviews
Product briefs
Schematic and layout files
Simulation models
Thermal and mechanical

Application notes

Application Note: Designing Embedded Systems for Testability

This document provides a context for using the features for manufacturability and debug implemented on Intel® processors and chipsets.

Version: 001 : October 2007
Application Note: Intel® ICH Family SPI Flash Programming Guide

This manual provides information about programming SPI flash on ICH family based platforms.

File Type/Size: PDF 929KB

Version: 2.4 : September 2008
Application Note: Serial Peripheral Interface (SPI) Flash Descriptor Configuration Checklist

This brief helps users understand how to implement Serial Peripheral Interface Flash and its uses in applications.

File Type/Size: PDF 280KB

Version: 1.0 : June 2008
Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies - White Paper

The findings of the Fiber Weave Work Group which investigated strategies for dealing with the negative signal integrity effects of fiberglass circuit boards.

File Type/Size: PDF 1,110KB

Version: 1.0 : November 2008
Impact of Halogen-free PCB Material - White Paper

Recommendations reflecting the impact of halogen-free material on PCB stackup and material properties.

File Type/Size: PDF 113KB
Intel® 5520 Chipset I/O Hub (IOH) 36D/24D Performance Optimization Guide

This technical white paper covers I/O hub performance optimizations for the platform based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: PDF 315KB

Version: 1.1 : February 2009
Intel® Xeon® 5500 Processor 5500 Series, Intel 5520 Chipset Intel® QuickPath Interconnect Frequency Select Update

Essential information on resetting the PLL frequency.

File Type/Size: PDF 331KB

Version: 1.0 : June 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S/1S Platform – Memory Performance White Paper

How to populate memory to achieve the best memory bandwidth performance.

File Type/Size: PDF 240KB

Version: 1.0 : December 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Platform, Improving Usability of Power Management Features

A user friendly menu that reduces complexity of BIOS power management.

File Type/Size: PDF 298KB

Version: 1.0 : November 2008
Memory 3 Sigma Power Analysis Technical White Paper

A new methodology of doing platform level memory power projection using statistical memory power data and showcases its benefit of achieving margin reduction on memory power projection.

File Type/Size: PDF 181KB

Version: 1.0 : March 2008
PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Considerations

An increase in the speed and frequency of a design combined with a need to reduce cost has created a challenge in defining an acceptable stack-up to meet the needs of high-speed designs.

Version: December 2008
Platform Software Optimization for Multi-Core Architecture Processors

Making a successful transition to multi-core architecture requires software optimization. This paper presents platform-level optimizations that resulted in significant performance gains.

File Type/Size: PDF 292KB

Version: May 2009
The New Intel® Xeon® Processor 5500 Series Catapults Processor Performance, Scalability, and Efficiency—A Huge Win for the Storage Industry

Intel® Xeon® processor provides a comprehensive set of advanced technologies for high performance storage applications.

File Type/Size: PDF 353KB

Version: 1 : June 2009
White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets

This paper discusses the software methods used to access PCI Express* registers, including the formula used to calculate the memory locations needed to access a specific register.

Version: December 2008
White Paper: Choosing the Right Storage Solution for Your Embedded Application

This paper examines storage solutions, from USB flash drives to high capacity disk drives, and discusses the trade-offs in finding the right solutions for an embedded application.

Version: December 2008
White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms

DDR is one of the challenging interfaces for a signal integrity engineer. This paper outlines an approach to divide the task, with an example for each step from the DDR2 interface.

Version: January 2009
White Paper: Designing Systems without a Suspend Supply

Here are recommendations for engineers who are designing embedded systems with the minimum number of power rails, including power and reset sequencing for standby and main rails.

Version: December 2008
White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles

This paper provides insights on how high speed signals behave on a board, the role played by inductors, resistors and capacitors and available design tools.

Version: January 2009
White Paper: First the Tick, Now the Tock: Next Generation Intel® Microarchitecture (Nehalem)

This white paper provides and introduction to the next generation Intel® Microarchitecture (Nehalem).

Version: 001 : April 2008
White Paper: Interfacing I²C Devices to Intel's SMBus Controller

I²C bus protocols can differ slightly from Intel® Controller Hub (ICH) SMBus protocols.This paper provides a full description of the details of each SMBus cycle supported by the ICH.

Version: January 2009
White Paper: JTAG 101

Information on the NEXUS automotive JTAG, the Intel XDP and ITP and available debuggers.

Version: January 2009
White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts

MSI delivery and servicing removes the two big limitations associated with Intel® architecture, the limited number of interrupts and unnecessarily high interrupt latencies.

Version: January 2009
White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines

Intel delivers platform design guidelines with validated platforms. This document details the signal integrity impacts from every deviation and describes solutions to overcome them.

Version: January 2009

Benchmarks

Dual Processor Server Platform Performance and Power Comparisons

This document compares previous generation performance per watt of (5000 and 5100 series platforms) to the Intel® Xeon® Processor 5500 Series.

File Type/Size: PDF 225KB

Version: 1.0 : January 2009
Performance Considerations and Tuning for the Intel® Xeon® 5500 Platform for Embedded Solutions

This paper presents performance related architecture topics for the Intel® Xeon® 5500 processor family to assist developers in designing a high performance embedded computer.

File Type/Size: PDF 3,334KB

Version: 1 : June 2009
White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization

L3 forwarding measures the Intel® architecture core capability in processing IP packets without any loss. This paper explains L3 forwarding measurement and optimization techniques.

Version: January 2009

Datasheets and specification updates

CK410B Clock Synthesizer/Driver Specification

This specification describes the CK410B clock synthesizer, which is a single-chip clock solution.

File Type/Size: PDF 1,200KB

Version: 1.0 : April 2006
Datasheet: Intel® I/O Controller Hub 10 (ICH10) Family

Datasheet for Original Equipment Manufacturers and BIOS vendors creating products based on the Intel® I/O Controller Hub 10 (ICH10) family.

Version: 003 : October 2008
Datasheet: Intel® 5520 Chipset and Intel® 5500 Chipset

Datasheet for the Intel® 5520 Chipset and Intel® 5500 Chipset.

Version: 001 : March 2009
Datasheet: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Datasheet

Version: 2.41 : April 2009
Datasheet: Intel® 82599 10 GbE Controller

Intel® 82599 10 Gigabit Ethernet Controller Datasheet

Version: 2.01 : July 2009
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 1

Datasheet for the Intel® Xeon® Processor 5500 Series – Vol. 1

Version: 001 : March 2009
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 2

Datasheet for the Intel® Xeon® Processor 5500 Series – Vol. 2

Version: 002 : April 2009
Intel® 5520 Chipset - Intel® Chipset Revision ID Selection

This document describes the implementation mechanism that allows the BIOS to select an appropriate CRID value to be read from the RID register.

File Type/Size: PDF 230KB

Version: 3.0 : January 2009
Intel® Advanced Server Management Interface (ASMI) Connector External Product Specification

ASMI-2 External Product Specification

File Type/Size: PDF 500KB

Version: 1.5 : April 2007
Intel® QuickPath Interconnect Electrical Specifications

Essential information about PHY layer electrical specifications.

File Type/Size: PDF 912KB

Version: 1.0 : July 2008
Intel® Xeon® Processor 5500 Series P-states Power Guidance

P-states are CPU performance states (power consumption & capability) within the C0 active/executing state of the processor.

File Type/Size: PDF 154KB

Version: December 2008
Specification Update: Intel® 5520 Chipset and Intel® 5500 Chipsets

Update to the specifications contained in the datasheet for the Intel® 5520 Chipset and Intel® 5500 Chipset.

Version: 006 : August 2009
Specification Update: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Specification Update

Version: 2.3 : May 2009
Specification Update: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Specification Update

Version: 2.0 : August 2009
Specification Update: Intel® 82801Jx I/O Controller Hub (ICH10)

Specification update for the Intel® ICH10 datasheet.

File Type/Size: PDF 261KB

Version: 1.0/Rev004 : December 2008
Specification Update: Intel® Xeon® Processor 5500 Series

Update to the specifications contained in the Intel® Xeon® Processor 5500 Series datasheet.

Version: 002 : April 2009

Design calculators, checklists and guides

Calculator: Intel® Core™ i7 Processor, Nehalem-EP Processors and LGA1366 Socket—Gen3 VRTT Loadline Validation Calculator Automation SW

Use the Gen3 VRTT Loadline Automation software in conjunction with the loadline validation spreadsheet and the Gen3 LGA1366 VRTT for processor voltage regulator evaluations.

File Type/Size: ZIP 9,719KB

Version: 1.01 : November 2008
Calculator: Intel® Xeon® Processor 5500 Series—LGA1366 Socket Loadline Validation Calculator for Gen3 VRTT

Loadline Validation Calculator Input Parameters for Vcore and VTT voltage regulator testing, tests include Static and Dynamic Regulation, dynamic VID, PSI#, ripple and thermal compensation.

File Type/Size: ZIP 2,751KB

Version: 2.0b : August 2009
Calculator: Intel® Quickpath Interconnect

This calculator enables platform designers to calculate Inte® QuickPath interconnect tap settings based on trace lengths and system topologies.

File Type/Size: application/octet-stream 67KB

Version: 1.0 : October 2007
Calculator: System Power Estimating for Sizing AC/DC Power Supplies

Calculator for estimating total system power for sizing the AC/DC power supply.

File Type/Size: application/octet-stream 541KB

Version: 4.0 : January 2009
DDR3 Trace Length Calculator

Calculator helps board designers meet the routing length matching requirements of the DDR3 interface as described in the latest Platform Design Guidelines.

File Type/Size: ZIP 1,614KB

Version: 1.71 : March 2009
Design Checklist

This document contains the platform design checklist which is based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 324KB

Version: 2.0 : March 2009
Design Guide: Intel® Xeon® Processor 5500 Series and Intel® 5520 Chipset Platform

Design guide with information supporting the use and implementation of the reference design.

File Type/Size: PDF 7,813KB

Version: 2.2 : September 2009
Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0

This document defines the electrical, thermal and mechanical design specifications for Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0.

Version: 002 : April 2008
Intel® Xeon® Processor 5500 Series Debug Handbook

This document helps customers debug common issues when powering on the platform.

File Type/Size: PDF 1,481KB

Version: 1.3 : December 2008
LGA771/LGA775 Version 2 Voltage Transient Tool (VTT)—Utility Software

VTT user guide, VTT manual host and VTT automation software including detailed instructions on setup, software installation, description of the software interface and tool errata.

File Type/Size: ZIP 14,849KB

Version: 7.5 : January 2008
LGA771/LGA775/LGA1366 Version 2 Voltage Transient Tool (VTT)—VRD 11.1 Platforms only—Utility Software

VTT user guide, manual host and automation software with detailed instructions on setup, software installation, description of the software interface and tool errata. VRD 11.1 Platforms only.

File Type/Size: ZIP 14,304KB

Version: 7.7 : January 2008
User Guide: Debug Port

Debug Port Design Guide (DPDG) targeted for external users and OEMs

File Type/Size: PDF 506KB

Version: 1.2 : April 2008
User Guide: Intel® QuickPath Interconnect – Serial Bus Validation Procedure

Training and methodology for serial bus validation.

File Type/Size: PDF 745KB

Version: 1.5 : December 2008
User Guide: Intel® Xeon® Processor 5500 Series LGA1366 Socket Daisy Chain Test Vehicle

This document outlines the electrical connections and provides detailed operational instructions.

File Type/Size: PDF 276KB

Version: 1.0 : September 2007
User Guide: Intel® Xeon® Processor 5500 Series Signal Integrity Model

This document describes the contents and usage of the models contained in 2S Processor HSPICE* signal integrity models.

File Type/Size: PDF 3,457KB

Version: 2.0 : February 2009
User Guide: Signal Integrity Support Tools for Advanced Interfaces

User guide with instructions for using the SISTAI application.

File Type/Size: PDF 2,551KB

Version: 1.1 : January 2009
User Guide: SPI Flash Usage

Guide for SPI flash usage prevents accidental or unauthorized flash reads/writes and guards against premature flash wear-out.

File Type/Size: PDF 143KB

Version: 1.1 : May 2008
User Guide: Validating Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

Describes the steps necessary to validate Intel® VT-d with an enabled BIOS.

File Type/Size: PDF 266KB

Version: 1.5 : November 2008

Development boards and kits

Get your software up and running using boards and development kits from Intel and third-party vendors.

Intel® Server Board S5400SF

A 1U rack-optimized, highly integrated server board designed to support Intel® Xeon® processors for high performance, high density computing.
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform CRB BIOS

BIOS for Intel Greencity (Server) and Silkcity (workstation) customer reference board based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 1,883KB

Version: March 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform CRB Greencity 12DIMM User Guide

User guide includes specifications and instructions to set up the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset reference board for certain operating systems.

File Type/Size: ZIP 2,741KB

Version: 1.5 : September 2008
User Guide: Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform Greencity Customer Reference Board

User guide includes specifications and instructions to set up the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset reference board for certain operating systems.

File Type/Size: ZIP 2,906KB

Version: 1.5 : September 2008
Where to Buy

Purchase Intel® embedded products from Intel® Authorized Industrial Distributors.
Additional Development Kits for Intel® Embedded

If you already have an account set up with Intel, contact your CBA for order placement. If you are not currently set up with Intel, visit the “Where to Buy” section of the EDC.

Ethernet controllers

Datasheet: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Datasheet

Version: 2.41 : April 2009
Datasheet: Intel® 82599 10 GbE Controller

Intel® 82599 10 Gigabit Ethernet Controller Datasheet

Version: 2.01 : July 2009
Intel® 82576 Gigabit Ethernet Controller Driver Download

Intel® 82576 Gigabit Ethernet Controller Driver Download
Intel® 82576 Gigabit Ethernet Controller—Boundary Scan Description Language (BSDL) Models

Intel® 82576 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.

File Type/Size: ZIP 7KB

Version: 2.2 : July 2008
Intel® 82599 10 Gigabit Ethernet Controller Silicon Development Kit

The 82599 Silicon Sample Kit is a zip file containing basic product information and tools that enable a customer to bring up a Silicon product sample during their validation or evaluation of the sample.
Intel® 82599 10 Gigabit Ethernet Controller—Boundary Scan Description Language (BSDL) File

Intel® 82599 10 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.

File Type/Size: ZIP 7KB

Version: 1.3 : June 2009
Product Brief: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Product Brief

Version: 001 : June 2008
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Product Brief

Version: 001 : March 2009
Specification Update: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Specification Update

Version: 2.3 : May 2009
Specification Update: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Specification Update

Version: 2.0 : August 2009

Platform overviews

Intel® QuickPath Interconnect Overview

This technical paper provides an overview of the Intel® QuickPath interconnect, which replaces the front-side bus.

File Type/Size: PDF 244KB

Version: 1.04
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Introduction

Watch this short video for a technical overview of Intel’s latest embedded platform. Duration: 3:33.
PECI 2.0 Feature Set Overview

Platform Environment Control Interface (PECI) training material to enable PECI 2.0 integration.

File Type/Size: PDF 266KB
Software Optimization for Intel® Multi-Core Processors

Intel® Microarchitecture (Nehalem) is the perfect fit for workloads associated with cryptography, transcoding, intrusion detection and more.

Product briefs

Product Brief: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Product Brief

Version: 001 : June 2008
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Product Brief

Version: 001 : March 2009
Product Brief: Intel® Xeon® 5500 Platform for Embedded Computing

Product brief for the Intel® Xeon® 5500 Platform for Embedded Computing.

Version: 002 : April 2009

Schematic and layout files

Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 12DIMM Archive

Schematic file archive for the CRB (12DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 79,375KB

Version: 1.5
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 12DIMM Board File

Board file for the CRB (12DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 15,049KB

Version: 1.5
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 12DIMM Schematics

Schematics for the CRB (12DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 1,044KB

Version: 1.5 : September 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 12DIMM Support Files

Support files for the CRB (12DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset including BOM, CPLD and changelist.

File Type/Size: ZIP 4,996KB

Version: 1.5
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 18DIMM Archive

Schematic file archive for the CRB (18DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 82,472KB

Version: 1.5
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 18DIMM Board File

Board file for the CRB (18DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 15,149KB

Version: 1.5
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 18DIMM Schematics

Schematics for the CRB (18DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset.

File Type/Size: ZIP 1,276KB

Version: 1.5 : September 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset 2S Platform - CRB Greencity 18DIMM Support Files

Support files for the CRB (18DIMM) based on the Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset including BOM, CPLD and changelist.

File Type/Size: ZIP 4,997KB

Version: 1.5 : September 2008

Simulation models

Intel IBIST Margin Test Presentation

This presentation covers the Intel® QuickPath Interconnect margining test.

File Type/Size: PDF 507KB

Version: 1.1 : May 2007
Intel® 5520 Chipset – Boundary Scan Description Language (BSDL) File

Boundary Scan Description Language (BSDL) files.

File Type/Size: ZIP 169KB

Version: 5.42 : July 2006
Intel® 5520 Chipset I/O Hub HSPICE* Signal Integrity Models

The model package contains the system reference clock model, PCI Express* and ESI model, miscellaneous I/O model, as well as the SilverDeck HSPICE* deck generation tool.

File Type/Size: ZIP 3,738KB

Version: 2.0
Intel® 5520 Chipset I/O Hub Signal Integrity Model User's Document

This document describes the contents and usage of the I/O Hub HSPICE* signal integrity model.

File Type/Size: PDF 1,360KB

Version: 2.0 : February 2009
Intel® 82801Jx I/O Controller Hub (ICH10) Consumer – I/O Buffer Information Specification (IBIS) Models

The I/O Buffer Information Specification Model defines a buffer’s characteristics for all of the I/O pins of the device.

File Type/Size: ZIP 5,033KB

Version: 1.0 : December 2007
Intel® Xeon® Processor 5500 Series 2S Processor HSPICE* Signal Integrity Models

The model package contains the QPI model suite, DDR3 model suites, the sideband signal models, as well as the SilverDeck HSPICE* deck generation tool.

File Type/Size: ZIP 9,667KB

Version: 2.0
Intel® Xeon® Processor 5500 Series Boundary Scan Description Language (BSDL) File

Boundary Scan Description Language (BSDL) files contain language code.

File Type/Size: ZIP 29KB

Version: 2.0 : March 2009
Interconnect BIST Pattern Generation and Checking Programming Guide

A primer on how to create a software based tool to do Intel IBIST pattern generation and checking.

File Type/Size: PDF 409KB

Version: 1.0 : September 2007
PCIe SR-IOV Topology Simulation

PCIe SR-I/O virtualization topology simulation

File Type/Size: ZIP 39,717KB

Version: 0.6

Thermal and mechanical

DDR3 RDIMM Thermal Test Module User's Guide

The user guide describes how to use the thermal test vehicle to test prototype thermal solutions, including mechanical attach and instrumentation of the test board.

File Type/Size: PDF 366KB

Version: 1.0 : November 2008
DDR3 RDIMM/UDIMM System Thermal Calculator

Calculator for registering Tj and hottest DRAM temperature based on various system thermal/mechanical boundary conditions and DIMM SPD thermal bytes information.

File Type/Size: ZIP 188KB

Version: 1.0
Intel® 5520 and Intel® 5500 Chipsets Thermal/Mechanical Design Guidelines

Thermal and mechanical operating limits and specifications for the Intel® 5520 and Intel® 5500 Chipsets and the reference thermal solutions that meet the specifications.

Version: 002 : March 2009
Intel® 5520 Chipset 36D/24D – Thermal and Mechanical Design Guide

The thermal and mechanical design guide contains system thermal design considerations and recommendations.

File Type/Size: PDF 1,663KB

Version: 2.0 : March 2009
Intel® 5520 Chipset I/O Hub (IOH) 36D Pinlist

This spreadsheet contains pin list information for the I/O Hub (IOH) 36D.

File Type/Size: application/octet-stream 599KB
Intel® 5520 Chipset I/O Hub 36D/24D Chipset Power Utility Program for 64-bit OS

This utility stresses the I/O hub to dissipate the worst-case power - for thermal solution and system cooling testing.

File Type/Size: ZIP 1,860KB

Version: 1.2 : February 2009
Intel® 5520 Chipset I/O Hub 36D/24D Short Heatsink ProE* Model

Mechanical models are ProE* and IGES* design files for enabled components for the optimized platform.

File Type/Size: ZIP 914KB

Version: 1.0
Intel® 5520 Chipset I/O Hub 36D/24D Tall Heatsink ProE* Model

Mechanical models are ProE* and IGES* design files for enabled components for the optimized platform.

File Type/Size: ZIP 1,823KB

Version: 1.0
Intel® 5520 Chipset I/O Hub Power Utility

This utility will stress the I/O hub to dissipate the worst-case power for thermal solution and system cooling testing.

File Type/Size: ZIP 2,253KB

Version: 1.2
Intel® 5520 Chipset Package and Heatsink FloTHERM* Models

Thermal models are used in commercially available Computational Fluid Dynamics thermal analysis tools. It contains the thermal models for the chipset/processor package and the reference heat sink assembly. It consists of a processor package and a socket assembly. The die, C4 attach, substrate, socket body, and BGA layer are modeled as blocks with orthotropic properties, the die power is modeled in one source sized and located so that it captures the power density effects of the processor.

File Type/Size: ZIP 42KB

Version: 1.0 : November 2007
Intel® 5520 Chipset Package and Heatsink Icepak* Models

Thermal models are used in commercially available Computational Fluid Dynamics thermal analysis tools. It contains the thermal models for the chipset/processor package and the reference heat sink assembly. It consists of a processor package and a socket assembly. The die, C4 attach, substrate, socket body, and BGA layer are modeled as blocks with orthotropic properties, the die power is modeled in one source sized and located so that it captures the power density effects of the processor.

File Type/Size: ZIP 38KB

Version: 1.0
Intel® 5520 Chipset Strap Pinlist

This document contains the strap describes all strap pins of the platform I/O hub with recommended connections.

File Type/Size: ZIP 9KB

Version: 2.0 : March 2009
Intel® 82801Jx I/O Controller Hub (ICH10) – Thermal Models

Thermal models are used in commercially available Computational Fluid Dynamics thermal analysis tools. It contains the thermal models for the chipset/processor package and the reference heat sink assembly. It consists of a processor package and a socket assembly. The die, C4 attach, substrate, socket body, and BGA layer are modeled as blocks with orthotropic properties, the die power is modeled in one source sized and located so that it captures the power density effects of the processor.

File Type/Size: ZIP 270KB

Version: 0.5 : August 2007
Intel® 82801Jx I/O Controller Hub (ICH10)—Ballout, Signal, and Mechanical Package

Mechanical package details, schematics, reference layout and drop-in core layout.

File Type/Size: ZIP 370KB

Version: 0.73
Intel® I/O Controller Hub 10 (ICH10) – Thermal and Mechanical Design Guide

The guide contains recommendations to aid system designers in the proper implementation of thermal management solutions which ensure reliable and efficient operations of Intel products. It outlines the operating limits of the product and discusses a generic thermal solution and suggests proper thermal design techniques based on a particular configuration and system boundary conditions and assumptions of platform power, maximum ambient and skin temperature, system size and feature set.

File Type/Size: PDF 1,027KB

Version: 2.0 : June 2008
Intel® Xeon Processor 5500 Series Processor Power Thermal Utility - Linux Version

Software that exercises the CPU for power and thermal evaluation by enabling the processor to run at power settings up to and including 100 percent.

File Type/Size: application/x-gzip 1,698KB
Intel® Xeon® Processor 5500 Series Electrical, Mechanical, and Thermal Specification (EMTS)

This document contains latest electrical, mechanical, and thermal specifications for Intel® Xeon® 5500 series (Nehalem-EP) processors.

File Type/Size: PDF 3,465KB

Version: 2.0 : March 2009
Intel® Xeon® Processor 5500 Series Mechanical Model

Mechanical model and drawings.
Intel® Xeon® Processor 5500 Series Power Thermal Utility

Software that exercises the CPU cores for thermal evaluation. It enables the processor to run at various power settings up to and including 100 percent.

File Type/Size: ZIP 3,107KB

Version: 1.1
Intel® Xeon® Processor 5500 Series Thermal Introduction

This video focuses on the thermal specifications for the Embedded specific High Tcase Intel® Xeon® processor 5500 series used in AdvancedTCA systems requiring NEBS-3 compliance. Duration: 6:29.
Intel® Xeon® Processor 5500 Series Thermal Model

Thermal model for the Intel® Xeon® Processor 5500 series, including user guide, 1U and 2U FloTHERM* models.

File Type/Size: ZIP 18KB

Version: .75 : September 2007
Intel® Xeon® Processor 5500 Series Thermal/Mechanical Design Guide

System and processor thermal design considerations and recommendations for platforms based on the Intel® Xeon® Processor 5500 series.

Version: 001 : March 2009
memBW4 Power Utility

This utility stresses the memory subsystem to dissipate the worst-case power for thermal solution and system cooling testing.

File Type/Size: ZIP 568KB

Version: 1.0
RDIMM TDP Calculator

This is a spreadsheet-based calculator for RDIMM TDP based on bandwidth input, DRAM power values and memory subsystem assumptions.

File Type/Size: ZIP 722KB

Version: 1.0
RDIMM Temperature Readout Utility

This utility will obtain both the real time temperature and critical temperature setting from each RDIMM on the CRB platform with only one processor installed.

File Type/Size: ZIP 988KB

Version: 1.1

Intel embedded graphics drivers
Migrating to Intel® Architecture

Software development tools
Software downloads
Technical documents

Intel embedded graphics drivers

Intel® Embedded Graphics Drivers (IEGD)

Intel® Embedded Graphics Drivers (IEGD) are a suite of multi-platform graphics drivers designed to meet the requirements of embedded applications.

Migrating to Intel® Architecture

AltiVec* SIMD Macros Translator

Read and accept the software agreement to download source code from N.A. Software. AltiVec* SIMD macros translator software is provided ‘as is.' Intel does not provide support. Please contact N.A. Software for support.
Design Guide: Implementing Firmware on Embedded Intel® Architecture Designs

This paper explores technical issues around building, debugging and deploying embedded firmware on an Intel® architecture system.

Version: January 2009
Tools For Moving AltiVec* DSP Applications to Intel® Processors - Presentation

Presentation introduces N.A. Software AltiVec* SIMD macros translator software. Software is provided ‘as is.’ Intel does not provide support.

File Type/Size: PDF 865KB

Version: April 2009

Software development tools

Intel® 82599 10 Gigabit Ethernet Controller Silicon Development Kit

The 82599 Silicon Sample Kit is a zip file containing basic product information and tools that enable a customer to bring up a Silicon product sample during their validation or evaluation of the sample.
QNX Neutrino* RTOS

The QNX Neutrino* RTOS provides a reliable microkernel architecture, robust memory protection, transparent networking, POSIX-based portability and a high-performance windowing system.
Wind River Linux 3.0* for Intel® Xeon® Processor 5500

Wind River Linux 3.0* is a commercial-grade Linux operating system for embedded device development based on Linux kernel 2.6.27 and GCC 4.3.2.
Wind River VxWorks* 6.7 for Intel® Xeon® 5500 Processor

VxWorks* platforms feature multi-core support capabilities within the operating system, network stack, and development tools to provide a development path to multi-core technology.

Software downloads

Intel® Embedded Graphics Drivers (IEGD)

Intel® Embedded Graphics Drivers (IEGD) are a suite of multi-platform graphics drivers designed to meet the requirements of embedded applications.
DDR Electrical Validation Parameter Utilities

DDR Electrical Validation Parameter Utilities enables DDR3 CPU Vref and timing margining. The user's guide has instructions on using the utilities and interpreting results.

File Type/Size: ZIP 6,336KB

Version: 1.2 : February 2009
Intel® 82576 Gigabit Ethernet Controller Driver Download

Intel® 82576 Gigabit Ethernet Controller Driver Download
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Platform Intel® QuickPath Interconnect – User Manual and Software

This is the Intel® QuickPath Interconnect Tool Kit (QTK) application for generating an Intel® Interconnect Built-In Self Test (IBIST) pattern to the QPI Load Board (QLB).

File Type/Size: ZIP 47,531KB

Version: 1.0 : May 2008
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Platform Validation Toolbox

A suite of test tools that run under Windows* operating systems containing the QPI CRC Error Monitor, C-state Residency Counter and CPU Memory ECC Monitor.

File Type/Size: ZIP 207KB

Version: 3.1 : December 2008
PECI 2.0 Test Software, Device Drivers and User Guide

This package contains the PECI 2.0 Test Exerciser software application tool for use with the PECI 2.0 test card and software device drivers for the baseboard of the PECI 2.0 test card. The Hardware & Software User Guide provides detailed instructions for software installation and hardware configuration for PECI system and device design using the PECI 2.0 test card.

File Type/Size: ZIP 25,728KB

Version: 1.0 : April 2008
VT-d Firmware Toolkit

Toolkit to verify target platform implementation of VT-d DMA Remapping (DMAR) Advanced Configuration and Power Interface ACPI tables and chipset configuration for VT-d.

File Type/Size: ZIP 37,695KB

Version: 1.1.1 : February 2009

Technical documents

Accelerating XML Processing with Intel® SSE4.2 to Improve Business Solutions

This white paper introduces the Intel® XML Software Suite and demonstrates how Intel® SSE4.2 instructions can be used to accelerate XML processing by 20 percent or more.

Version: November 2008
Accessing the Real Time Clock Registers and NMI Enable Bit—A Study in I/O Locations 0x70-0x77

This paper explains how I/O address aliasing works with respect to these registers for all ICH modes and provides exact programming instructions and sample code.

Version: January 2009
Application Note: Intel® ICH Family SPI Flash Programming Guide

This manual provides information about programming SPI flash on ICH family based platforms.

File Type/Size: PDF 929KB

Version: 2.4 : September 2008
Increasing Memory Throughput with Intel® Streaming SIMD Extensions 4 (Intel® SSE4) Streaming Load

This white paper shoes how the Intel® SSE4 Streaming Load instruction can be used to improve memory I/O throughput.

Version: November 2008
Intel® 5520 Chipset – XOR Test Mode

This document describes the XOR manufacturing test mode used to test the PCIe* interface.

File Type/Size: PDF 141KB

Version: 1.0 : April 2008
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.

Version: September 2009
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.

Version: September 2009
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.

Version: September 2009
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.

Version: September 2009
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 processors. Electronic versions allow you to quickly get to the information you need.

Version: September 2009
Intel® 82801Jx I/O Controller Hub (ICH10)—Testability Package

The In-Circuit Tester zip file contains a document that describes the XOR Chain test mode and enabling the JTAG interface, the in circuit test file, and the JTAG access file.

File Type/Size: ZIP 84KB

Version: 1.0 : June 2008
Intel® Instruction Set Architecture Leadership 2009 and Beyond

This presentation from IDF 2008 discusses the Intel® SSE4.2 instruction.
Intel® Quick Path Architecture

This white paper provides to Intel® QuickPath Architecture, a new platform ingredient for using scalable shared memory to maximize the performance of processors based on Intel® microarchitecture (Nehalem).

Version: 001
Intel® Software Development Products White Papers

Browse dozens of technical white papers on Intel® Compilers, the Intel® VTune™ Analyzer, Intel® Performance Libraries, Threading Analysis Tools, Cluster Tools, and XML products.
Intel® SSE4 Programming Reference

Intel® Streaming SIMD Extensions 4 (SSE4) introduces 54 new instructions to improve the performance of media, imaging and 3D workloads in Intel® processors. (Nehalem-EP processor)

Version: 003 : July 2007
Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Server Platform Services Firmware Integration Guide

This document describes the integration process for server platform services (SPS) firmware (FW) implemented on the manageability engine of the Intel® 5520 chipset.

File Type/Size: PDF 1,108KB

Version: 1.0 : July 2008
Intel® Xeon® Processor 5500 Series Intel® Turbo Boost Technology Update

This presentation provides an overview of Intel® Turbo Boost Technology (previously known as Turbo Mode) on the Intel® Xeon® processor series.

File Type/Size: PDF 623KB

Version: February 2009
Introduction to Intel® Core™ i7

This audio/video presentation introduces the new features of the Intel® Core™ i7 processor family and the Intel® Core™ i7 platform. (Requires Flash) Note: this presentation describes platform features and software applicable to the Intel® microarchitecture (Nehalem), shared by Intel Core i7 processors and by Intel® Xeon® 5500 processors for embedded computing.
Motion Estimation with Intel® SSE4

This white paper describes how to optimize motion estimation algorithms using Intel® SSE4 instructions.

Version: April 2007
Platform Software Optimization for Multi-Core Architecture Processors

Making a successful transition to multi-core architecture requires software optimization. This paper presents platform-level optimizations that resulted in significant performance gains.

File Type/Size: PDF 292KB

Version: May 2009
Tuning your Application for the Intel® Microarchitecture (Nehalem) Family

This presentation contains the best-known methods for maximizing software performance with processors based on Intel® Microarchitecture (Nehalem). (Requires Flash) Note: this presentation describes platform features and software applicable to the Intel® Microarchitecture (Nehalem), shared by Intel Core i7 processors and by Intel® Xeon® 5500 Processors for embedded computing.
White Paper: JTAG 101

Information on the NEXUS automotive JTAG, the Intel XDP and ITP and available debuggers.

Version: January 2009

+ Intel® 82576 Gigabit Ethernet Controller

Overview

The Intel® 82576 Gigabit Ethernet Controller provides high performance dual-port gigabit connectivity in a multi-core platform, as well as in a virtualized platform. In a multi-core platform it supports technologies including Intel® QuickData Technology, MSI-X, and Low Latency Interrupts that help accelerate the movement of data across the platform, improving application response times. In a virtualized environment, it supports Intel® Virtualization Technology for Connectivity that helps improve I/O performance by reducing I/O overhead.

LAN features

PCI Express* 10/100/1000 Ethernet connection
Dual-port, single-chip configuration
Software virtualization layer reduces I/O overhead
Direct connectivity to virtual machines for Pnear-native performance and data protection
Enhanced support for pass-through traffic to the board management controller
Extended 7-year lifecycle support

Documents & tools

Datasheet: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Datasheet

Version: 2.41 : April 2009
Intel® 82576 Gigabit Ethernet Controller Driver Download

Intel® 82576 Gigabit Ethernet Controller Driver Download
Intel® 82576 Gigabit Ethernet Controller—Boundary Scan Description Language (BSDL) Models

Intel® 82576 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.

File Type/Size: ZIP 7KB

Version: 2.2 : July 2008
Product Brief: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Product Brief

Version: 001 : June 2008
Specification Update: Intel® 82576 Gigabit Ethernet Controller

Intel® 82576 Gigabit Ethernet Controller Specification Update

Version: 2.3 : May 2009

+ Intel® 82599 10 GbE Controller

Overview

The Intel® 82599 10 Gigabit Ethernet controller and Intel® Xeon® processor 5500Δ series-based servers deliver unmatched performance scalability in the data center. The Intel 82599 10 gigabit Ethernet controller includes Intel® Virtualization Technology for Connectivity (Intel VT-c) to deliver outstanding performance in virtualized server environments. The controller reduces cost and complexity of the data center by combining LAN and SAN traffic onto a single Ethernet fabric. Customers can use iSCSI, NAS or FCoE to carry storage traffic over Ethernet. In order to meet SAN requirements for guaranteed packet delivery, the controller implements capabilities including enhanced transmission selection and priority flow control. This controller is deal for embedded applications in telecommunications infrastructure, industrial, medical, military, interactive client, infotainment, and print imaging applications.

LAN features

Receive Side Coalescing, Intel® Ethernet Flow Director, and support for PCI Express* 2.0
Intel® Virtualization Technology for Connectivity (Intel® VT-c) for I/O virtualization
Support for lossless Ethernet, iSCSI acceleration, NAS, and Fibre Channel over Ethernet (FCoE) offloads to help consolidate data center networks onto a single Ethernet fabric
Extended 7-year lifecycle support

Documents & tools

Datasheet: Intel® 82599 10 GbE Controller

Intel® 82599 10 Gigabit Ethernet Controller Datasheet

Version: 2.01 : July 2009
Intel® 82599 10 Gigabit Ethernet Controller Silicon Development Kit

The 82599 Silicon Sample Kit is a zip file containing basic product information and tools that enable a customer to bring up a Silicon product sample during their validation or evaluation of the sample.
Intel® 82599 10 Gigabit Ethernet Controller—Boundary Scan Description Language (BSDL) File

Intel® 82599 10 Gigabit Ethernet Controller Boundary Scan Description Language models for board level scan testing. Models describe boundary scan chain internal to the processor.

File Type/Size: ZIP 7KB

Version: 1.3 : June 2009
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Product Brief

Version: 001 : March 2009
Specification Update: Intel® 82599 10 Gigabit Ethernet Controller

Intel® 82599 10 Gigabit Ethernet Controller Specification Update

Version: 2.0 : August 2009

Embedded
Design Center

Find it fast

Use this tool to quickly refine your search by selecting a topic and document type by keyword only. Learn more

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Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Formerly code named: Tylersburg-EP (Nehalem-EP + Tylersburg-36D)

+ Specifications

+ Platform highlights

Intel® Xeon® Processor 5500 Series for Embedded Computing

Application notes

Benchmarks

Datasheets and specification updates

Design calculators, checklists and guides

Development boards and kits

Ethernet controllers

Platform overviews

Product briefs

Schematic and layout files

Simulation models

Thermal and mechanical

Intel embedded graphics drivers

Migrating to Intel® Architecture

Software development tools

Software downloads

Technical documents

+ Intel® 82576 Gigabit Ethernet Controller

Overview

LAN features

Documents & tools

+ Intel® 82599 10 GbE Controller

Overview

LAN features

Documents & tools

Design resources

Intel® Xeon® Processor 5500 Series Thermal Introduction Video

Related ecosystem board solutions

Intel® Embedded Alliance is a trusted supply line of Intel-based products and services where member companies offer solutions to speed development, design and reduce costs.

+ Other Intel®-EDC-supported platforms

EmbeddedDesign Center

Find it fast Use this tool to quickly refine your search by selecting a topic and document type by keyword only. Learn more

Need more help?

Intel® Xeon® Processor 5500 Series and the Intel® 5520 Chipset Formerly code named: Tylersburg-EP (Nehalem-EP + Tylersburg-36D)

+ Specifications

+ Platform highlights

Intel® Xeon® Processor 5500 Series for Embedded Computing

Application notes

Benchmarks

Datasheets and specification updates

Design calculators, checklists and guides

Development boards and kits

Ethernet controllers

Platform overviews

Product briefs

Schematic and layout files

Simulation models

Thermal and mechanical

Intel embedded graphics drivers

Migrating to Intel® Architecture

Software development tools

Software downloads

Technical documents

+ Intel® 82576 Gigabit Ethernet Controller

Overview

LAN features

Documents & tools

+ Intel® 82599 10 GbE Controller

Overview

LAN features

Documents & tools

Design resources

Intel® Xeon® Processor 5500 Series Thermal Introduction Video

Related ecosystem board solutions Intel® Embedded Alliance is a trusted supply line of Intel-based products and services where member companies offer solutions to speed development, design and reduce costs.

+ Other Intel®-EDC-supported platforms

Embedded
Design Center

Find it fast

Use this tool to quickly refine your search by selecting a topic and document type by keyword only. Learn more

Related ecosystem board solutions

Intel® Embedded Alliance is a trusted supply line of Intel-based products and services where member companies offer solutions to speed development, design and reduce costs.