Update the operating system related code for Intel architecture
Whether the current and target OS are the same or different, device drivers, libraries and software development tools need to be surveyed to determine their availability for Intel architecture.
- Intel® Embedded Graphics Drivers
- Intel® embedded chipset drivers: standard desktop, mobile and server chipset drivers for Microsoft* (XP or Vista*)
- Board support packages (BSPs) for RTOSs are provided by the RTOS vendor.
- Board support packages (BSPs) for Microsoft* Windows CE, can be downloaded from these third-party vendors’ sites:
- – Adeneo Corporation*
- – BSQUARE*
- – Wipro Technologies*
If any device drivers or libraries are developed in-house, they will need to be rewritten for Intel architecture.
If any third-party drivers or libraries are required, check with the third-party vendor for equivalent Intel architecture products.
Development tools for Intel architecture: See the Intel® Software Development Products section for information about Intel tools and visit the products’ websites for information on OS support. On-chip debugging tools for Intel architecture are supported by American Arium* or Macraigor* Systems LLC (February 2009).
Choose the method for system initialization
BIOS – Choose BIOS and/or UEFI firmware if the design will support multiple standard interfaces and expansion slots, or a host mainstream OS with a broad set of pre-OS features, that is ready to run multiple applications.
Boot Loader – Choose a boot loader for minimal or specialized firmware stacks where requirements might include optimization for speed, size or specific system requirements, and will support minimal upgrade or expansion capabilities. QNX* Fastboot Technology is available for Intel® Atom™ processors.
Embedded Intel architecture designs include a firmware stack that initializes CPU cores, memory, IO, peripherals and graphics and provides runtime support for operating systems. See this white paper for an overview of these firmware technologies: Implementing Firmware on Embedded Intel® Architecture Designs.
If any part of the code is written in assembly language, update it for Intel architecture instructions
Basic assembly instructions – Manually update the basic assembly instructions using the Intel® 64 and IA-32 Architectures Software Developer's Manuals.
Vector oriented code solutions – Manually update vector oriented code using the AltiVec/SSE Migration Guide published by Apple*.
Translate the vector oriented code using the N.A.Software*/PowerPC*/AltiVec* to Intel®/SSE conversion tools:
Vector Signal Image Processing Library (VSIPL) – This is highly efficient computational middleware for signal and image processing applications. VSIPL is an open standard for embedded signal and image processing software and hardware vendors. It abstracts hardware implementation details; applications are portable across processor types and generations without rewriting the software. This tool will be available as the VSIPL library, or as C-VSIPL, the plain “C” equivalent for in-house libraries that need to be converted. N.A.Software will also port custom in-house DSP libraries to Intel architecture.
AltiVec.h include file for Intel® architecture – This is the same as PPC AltiVec.h, but targets the Intel® SSE instruction set instead of AltiVec. The application’s DSP code remains unchanged.
AltiVec assembler to Intel® assembler-compiler – This tool converts relatively small blocks of PPC AltiVec assembler into C code, which can then be compiled into SSE assembler code. This tool is currently under development.
Does the software abstract the memory architecture of the processor?
Yes – The code is endian-neutral. No changes are required.
No – The code will need to be updated for little-endian memory architecture. Manually update the endianness differences in the code. Use Intel’s Endianness White Paper as a guide to the required changes.
Table 1. Differences Between PPC and Intel® Hardware Architecture
| Instruction Set |
| Instructions |
PPC and Intel® architecture instructions are very different. For some instructions there is no one-to-one (PPC to Intel® architecture) equivalent. Refer to the Intel® Software Developer Manuals and instruction set information and tools that may assist the assembly code migration.
|
| Alignment |
PPC instructions are all 4 bytes in size and must be aligned on 4-byte boundaries. Intel® architecture instructions vary in size and therefore do not require alignment.
On PPC a bool is 4 bytes. On Intel® architecture, a bool is 1 byte. Make the code portable by changing the PPC boolean data to an unsigned 32-bit integer.
|
| Vector oriented instructions |
PPC uses AltiVec* instructions. Intel® architecture uses streaming SIMD extensions (SSE). Refer to the Vector Oriented Code section for details about migrating AltiVec to SSE instructions.
|
| Operations |
| Divide-by-zero |
For integer divide-by-zero, PPC simply returns zero. On Intel® architecture, executing this operation is fatal. Code should always check the denominator for zero before executing the divide operation. There is no difference in operation between PPC and Intel® architecture floating point divide-by-zero.
|
| Hardware Devices |
| Drivers and libraries |
If a PPC driver or library comes from a third-party vendor, check with the vendor for equivalent Intel® architecture products. If any device drivers or libraries are developed in-house, they will need to be rewritten for Intel® architecture.
Refer to the Device Drivers section of PowerPC* to Intel® Architecture Migration for chipset and graphics driver information.
|
| Registers |
| Calling
conventions specified by the application binary interface (ABI) |
Arguments are passed in registers for PPC. For Intel® architecture, arguments are passed on the stack.
Intel® architecture has fewer registers than PPC and therefore local variables may be stored on the stack as well.
|
| Memory |
| Byte order (endianness) |
Endianness describes how multi-byte data is represented by a computer system and is dictated by the CPU architecture of the system. Intel® architecture uses little endian and PPC uses big endian format to store multi-byte data. The difference in endian architecture is an issue when software or data is shared between computer systems. Refer to the Endianness section of PowerPC* to Intel® Architecture Migration for more information.
|
| Bit fields |
The order of bit fields in memory can be reversed between architectures. Refer to the Bit Fields and Bit Masks section of the endianness white paper for more details.
|
For further reference, see:
"Architectural Differences." Universal Binary Programming Guidelines. 26 Feb 2007. Apple.com. 18 Dec 2008.