12th Generation Intel® Core™ Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 655258 | 06/15/2023 | Public |
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Revision History
Introduction
Technologies
Power Management
Thermal Management
Memory
USB-C* Sub System
PCIe* Interface
Direct Media Interface and On Package Interface
Graphics
Display
Camera/MIPI
Signal Description
Electrical Specifications
Package Mechanical Specifications
CPU And Device IDs
Security Technologies
Intel® Trusted Execution Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection
Intel® Supervisor Mode Access Protection
Intel® Secure Hash Algorithm Extensions
User Mode Instruction Prevention
Read Processor ID
Intel® Total Memory Encryption - Multi-Key
Intel® Control-flow Enforcement Technology
KeyLocker Technology
Devil’s Gate Rock
Power and Performance Technologies
Intel® Smart Cache Technology
IA Cores Level 1 and Level 2 Caches
Ring Interconnect
Intel® Performance Hybrid Architecture
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology 2.0
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology
Intel® GMM and Neural Network Accelerator
Cache Line Write Back
Remote Action Request
User Mode Wait Instructions
Power Management
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor AUX Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Rest Of Platform (ROP) PMIC
PCI Express* Power Management
TCSS Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
Memory Controller Power Gate
System Memory Controller Organization Mode (DDR4/5 Only)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5/x Ascending and Descending
LPDDR4x CMD Mirroring
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Signal Description
System Memory Interface
PCI Express* Graphics (PEG) Signals
Direct Media Interface (DMI) Signals
Reset and Miscellaneous Signals
Display Interfaces
USB Type-C Signals
MIPI* CSI-2 Interface Signals
Processor Clocking Signals
Testability Signals
Error and Thermal Protection Signals
Power Sequencing Signals
Processor Power Rails
Ground and Reserved Signals
Processor Internal Pull-Up / Pull-Down Terminations
Processor Interfaces DC Specifications
DDR4 DC Specifications
DDR5 DC Specifications
LPDDR4x DC Specification
LPDDR5 DC Specification
PCI Express* Graphics (PEG) Group DC Specifications
Digital Display Interface (DDI) DC Specifications
CMOS DC Specifications
GTL and OD DC Specification
PECI DC Characteristics
Power Training
BIOS MRC performing Power Training steps to reduce DDR I/O power while keeping reasonable operational margins still guaranteeing platform operation. The algorithms attempt to weaken ODT, driver strength and the related buffers parameters both on the MC and the DRAM side and find the best possible trade-off between the total I/O power and the operating margins using advanced mathematical models.