Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795262 | 12/14/2023 | 001 | Public |
ACPI Control (ACTL) – Offset 1bd8
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:8 | 0h | RO | Reserved |
| 7 | 0h | RW | ACPI Enable (EN) When set, decode of the I/O range pointed to by the ACPI base register is enabled and the ACPI power management function is enabled. |
| 6:3 | 0h | RO | Reserved |
| 2:0 | 0h | RW | SCI IRQ Select (SCIS) Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ[9-11], and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20-23, and can be shared with other interrupts. |