Alternate Protocol Selective Enable Mask Register (APSEMR) – Offset b20 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This is the Alternate Protocol Selective Enable Mask Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:1	0h	RW/P	Alternate Protocol Selective Enable Mask - Others (APEMO) Other bits in this register represent protocols other than PCI Express. The default values of these other bits is implementation specific. The width of this field is shown here as 32 bits. The actual width derpends on Alternate Protocol Count. Bits in this field corresponding to disabled Alternate Protocol Index values are permitted to be hardwired to 0b. Bits in this field corresponding to Alternate Protocol Index Select values above Alternate Protocol Count are permitted to be hardwired to 0b.
0	1h	RW/P	Alternate Protocol Selective Enable Mask - PCI Express (APEMPCIE) The PCI Express Protocol is always index 00h. The default value of this bit is 1b (i.e., PCI Express is always enabled by default). This bit is permitted to be hardwired to 1b.

Bit Range

Default

Access

Field Name and Description

31:1

RW/P

Alternate Protocol Selective Enable Mask - Others (APEMO)

Other bits in this register represent protocols other than PCI

Express. The default values of these other bits is implementation specific. The width of this field is shown here as 32 bits. The actual width derpends on Alternate Protocol Count. Bits in this field corresponding to disabled Alternate Protocol Index values are permitted to be hardwired to 0b. Bits in this field corresponding to Alternate Protocol Index Select values above Alternate Protocol Count are permitted to be hardwired to 0b.

RW/P

Alternate Protocol Selective Enable Mask - PCI Express (APEMPCIE)

The PCI Express Protocol is always index 00h. The default value of this bit is 1b (i.e., PCI Express is always enabled by default).

This bit is permitted to be hardwired to 1b.

Multicast Extended Capability Header (MCECH)

Alternate Protocol Data 2 Register (APD2R) Multicast Extended Capability Header (MCECH)