31

0h

RW

CSME Power Gated Qualification Disable (MEPGQDIS)

0 = SLP_​S0# assertion requires CSME to be power gated

1 = SLP_​S0# assertion does not require CSME to be power gated

30

0h

RW

GbE Disconnected Qualification Disable (GBEDISCQDIS)

0 = SLP_​S0# assertion requires GbE LAN to be disconnected

1 = SLP_​S0# assertion does not require GbE LAN to be disconnected

29

0h

RW

Audio DSP in D3 Qualification Disable (ADSPD3QDIS)

0 = SLP_​S0# assertion requires the Audio DSP controller to be in D3

1 = SLP_​S0# assertion does not require the Audio DSP controller to be in D3

28

0h

RW

XHCI in D3 Qualification Disable (XHCID3QDIS)

0 = SLP_​S0# assertion requires the XHCI controller to be in D3

1 = SLP_​S0# assertion does not require the XHCI controller to be in D3

27

0h

RO

Reserved

26

0h

RW

Thermal Sensor Disable Qualification Disable (TSDQDIS)

0 = SLP_​S0# assertion requires the thermal sensor to be disabled

1 = SLP_​S0# assertion does not require the thermal sensor to be disabled

25

0h

RW

ICC PLL Wake Block Enable (ICCPLLWBE)

0 = PMC HW never blocks ICLK PLL from being re-enabled during a dynamic ICC PLL shutdown event.

1 = PMC HW blocks ICLK PLL from being re-enabled for any reason following a dynamic ICC PLL shutdown event while SLP_​S0# assertion conditions are met and until VR idle mode exit timer expires after SLP_​S0# de-assertion.

24

0h

RO

Reserved

23

0h

RW

Power Ungate Block Enable (PUGBEN)

0 = PMC HW does not block ME and modphy Power from being restored upon being requested to do so while SLP_​S0# assertion conditions are met and until VR idle mode exit timer expires after SLP_​S0# de-assertion.

1 = PMC HW blocks ME and modphy Power from being restored upon being requested to do so while SLP_​S0# assertion conditions are met and until VR idle mode exit timer expires after SLP_​S0# de-assertion.

22

0h

RW

24MHz Crystal Shutdown Qualification Disable (XTALSDQDIS)

0 = SLP_​S0# assertion requires the 24MHz Crystal Oscillator to be shutdown. Once SLP_​S0# is asserted, the Crystal oscillator should be kept off until PMC notifies it is allowed to be re-enabled.

1 = SLP_​S0# assertion does not require the 24MHz Crystal to be shutdown.

21:16

0h

RW

SRC[5:0]CLKRQ# VR Idle Enable (CLKRQ_​VRI_​EN)

Each bit in this register deterimes whether the corresponding PCIe clock request pin (SRC[bit #]CLKRQ#) is enabled as a VR Idle break event / entry inhibitor.

For example, if CLKRQ_​VRI_​EN[0] = '1' then SRC0CLKRQ# must be a '1' in order for SLP_​S0# to be asserted and if SRC0CLKRQ# goes to '0' then it will cause SLP_​S0# to be deasserted. On the other hand, if CLKRQ_​VRI_​EN[0] = '0' then the state of SRC0CLKRQ# has no impact on SLP_​S0#.

15:14

0h

RO

Reserved

13

0h

RW

SLP_​S0# Low Voltage Mode Enable (SLPS0LVEN)

0 = high speed ring oscillator (>24MHz) clocks are allowed to run when SLP_​S0#=0

1 = high speed ring oscillator (>24MHz) clocks are not allowed to run when SLP_​S0#=0.
PMC must prevent ungating of these clock domains while SLP_​S0#=0.

12

0h

RW

Intel® Trace Hub AON Active Request Qualification Disable (NPKAONACTREQQDIS)

0 = SLP_​S0# assertion requires Intel® Trace Hub not to be requesting AON active
1 =SLP_​S0# assertion does not require Intel® Trace Hub not to be requesting AON active.

11:9

0h

RW

SLP_​S0# Minimum Assertion Width (SLP_​S0_​MIN_​ASST_​WDTH)

000 = 30.5us
001 = 61us
010 = 91.5us
011 = 122us
100 = 152.5us
101 = 183us
110 = 500us
111 = 1ms

8:0

0h

RW

SLP_​S0# De-assertion Exit Latency (SLP_​S0_​EXIT_​LAT)

This value is used in the SLP_​S0# exit timer and has an RTC clk period (30.5us) granularity.
000h = 0us (reserved)
001h = 30.5us
002h = 61us
003h = 91.5us
...
1FFh = 15.6ms