Data Link Feature Capabilities Register (DLFCAP) – Offset a94 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This is the Data Link Feature Capabilities Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31	1h	RW/O	Data Link Feature Exchange Enable (DLFEE) If set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b. Register Attribute: Static.
30:23	0h	RO	Reserved
22:1	0h	RW/O	Local Feature Supported (LFS) These bits indicate that the Downstream Port supports the associated Data Link Feature. For this version of this specification, this field is hardwired to 0. Register Attribute: Static.
0	1h	RW/O/P	Local Scaled Flow Control Supported (LSFCS) This bit indicates that the Port supports the Scaled Flow Control Feature. Register Attribute: Static.

Data Link Feature Status Register (DLFSTS)

Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Status Register (DLFSTS)