Link Control Register (LNKCTL) – Offset 90 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

Bit Range	Default	Access	Field Name and Description
15:8	0h	RO	RESERVED (RSVD) RESERVED
7	0h	RW	Extended Synch (ES) When Set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state. Not supported. This bit is not connected to any logic.
6	1h	RW	Common Clock Configuration (CCC) When Set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. This bit is not connected to any logic.
5	0h	RO	Retrain Link (RL) A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. This bit is not applicable and is Reserved for Endpoints
4	0h	RO	Link Disable (LD) This bit disables the Link by directing the LTSSM to the Disabled state when Set. This bit is Reserved on Endpoints
3	0h	RO	Read completion boundary (RCB) Optionally Set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Defined encodings are: 0b 64 byte 1b 128 byte
2	0h	RO	Reserved (RSVD_1) Reserved
1:0	0h	RW	Active State Power Management (ASPM) Control (ASPMC) This field controls the level of ASPM enabled on the given PCI ExpressLink.Defined encodings are: 00b Disabled 01b L0s Entry Enabled 10b L1 Entry Enabled 11b L0s and L1 Entry Enabled This bit is not connected to any logic.

Link Capabilities Register (LNKCAP) Link Status Register (LNKSTS)