Physical Layer 16.0 GT/s Status Register (PL16S) – Offset aa8 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This is the Physical Layer 16.0 GT/s Status Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:5	0h	RO	Reserved (RSVD_M) Reserved
4	0h	RW/1C/V/P	Link Equalization Request 16.0 GT/s (LERG4) This bit is Set by hardware to request the 16.0 GT/s Link equalization process to be performed on the Link. The default value of this bit is 0b.
3	0h	RO/V/P	Equalization 16.0 GT/s Phase 3 Successful (EQP3SG4) When set to 1b, this bit indicates that Phase 3 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. The default value of this bit is 0b. Register Attribute: Static.
2	0h	RO/V/P	Equalization 16.0 GT/s Phase 2 Successful (EQP2SG4) When set to 1b, this bit indicates that Phase 2 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. The default value of this bit is 0b. Register Attribute: Static.
1	0h	RO/V/P	Equalization 16.0 GT/s Phase 1 Successful (EQP1SG4) When set to 1b, this bit indicates that Phase 1 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. The default value of this bit is 0b. Register Attribute: Static.
0	0h	RO/V/P	Equalization 16.0 GT/s Complete (EQG4) When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 16.0 GT/s data rate has completed. The default value of this bit is 0b. Register Attribute: Static.

Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)

Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)