Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795262 | 12/14/2023 | 001 | Public |
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) – Offset adc
This is the Physical Layer 32.0 GT/s Extended Capability Header registers. Refer description for each individual field below for more details of the register functionality.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:20 | 0h | RO | Next Capability Offset (NCO) This field contains the offset to the next PCI Express Capability |
| 19:16 | 0h | RO | Capability Version (CV) This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. |
| 15:0 | 0h | RO | PCI Express Extended Capability ID (ECID) This field is a PCISIG defined ID number that indicates the nature and format of the Extended Capability. |