Power Scheduler Control-1 (PWR_SCHED_CTRL2) – Offset 8144 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

These bit enable by EP type those EPs classes that are considered for determining next periodic active interval for pre-wake of
the periodic_active signal. EP classes that are disabled may never be observed in setting of the periodic_active signal.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RW	Reserved (RSVD0) Reserved
26	0h	RW	Disable Power Scheduler wait for inprogress NDE (DISABLE_INPROG_NDE_WAIT) Policy for controlling transition of LTR_STATE_* FSM to move from ACTIVE to _INACTIVE states 0: LTR_STATE_ FSM will wait for inprogress NDE message to complete before transitioning to one of the INACTIVE states 1: LTR_STATE_* FSM will not wait for inprogress NDE message to complete before transitioning to one of the INACTIVE states
25	0h	RW	Disable sending NDE sideband messages with NoREQ (NDE_SBMSG_NOREQ_DIS) Policy to disable sending NOREQ NDE sideband messages 0: Controller will send NOREQ NDE sideband messages 1: Controller will not send NOREQ NDE sideband messages
24:0	0h	RO	Reserved

AUX Power Management Control (AUX_CTRL_REG2)

Power Scheduler Control-0 (PWR_SCHED_CTRL0) AUX Power Management Control (AUX_CTRL_REG2)