Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) – Offset aec - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This is the Receiver Modified TS Data 1 Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO/V	Received Modified TS Vendor ID (RCVDMTSVID) If Modified TS Received is Set, this field contains the Modified TS Vendor ID field from the Modified TS1/TS2 Ordered Set received If Modified TS Received is Clear, this field contains 0000h. Bits 15:8 contain the value of Symbol 10. Bits 7:0 contain the value of Symbol 11. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0000h.
15:3	0h	RO/V	Received Modified TS Information 1 (RCVDMTSINFO1) If Modified TS Received is Set, this field contains the Modified TS Information 1 field from the Modified TS1/TS2 Ordered Set If Modified TS Received is Clear, this field contains 0 0000 0000 0000b. Bits 15:8 contain the value of Symbol 12. Bits 16:8 contain the value of Symbol 13. Bits 7:0 contain the value of Symbol 14. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0 0000 0000 0000b.
2:0	0h	RO/V	Received Modified TS Usage Mode (RCVDMTSUSAGEMD) If Modified TS Received is Set, this field contains the Modified TS Usage field from the Modified TS1/TS2 Ordered Set If Modified TS Received is Clear, this field contains 000b. Unused bits in this field are permitted to he hardwired to 0b. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 000b.

Bit Range

Default

Access

Field Name and Description

31:16

RO/V

Received Modified TS Vendor ID (RCVDMTSVID)

If Modified TS Received is Set, this field contains the Modified TS Vendor ID field from the Modified TS1/TS2 Ordered Set received

If Modified TS Received is Clear, this field contains 0000h.

Bits 15:8 contain the value of Symbol 10.

Bits 7:0 contain the value of Symbol 11.

If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0000h.

15:3

RO/V

Received Modified TS Information 1 (RCVDMTSINFO1)

If Modified TS Received is Set, this field contains the Modified TS Information 1 field from the Modified TS1/TS2 Ordered Set

If Modified TS Received is Clear, this field contains 0 0000 0000 0000b.

Bits 15:8 contain the value of Symbol 12.

Bits 16:8 contain the value of Symbol 13.

Bits 7:0 contain the value of Symbol 14.

If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0 0000 0000 0000b.

2:0

RO/V

Received Modified TS Usage Mode (RCVDMTSUSAGEMD)

If Modified TS Received is Set, this field contains the Modified TS Usage field from the Modified TS1/TS2 Ordered Set

If Modified TS Received is Clear, this field contains 000b.

Unused bits in this field are permitted to he hardwired to 0b. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 000b.

Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)

Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)