31

0h

RO/V

XHCI SMI Status (XHCI_​SMI_​STS)

This bit will be set when any USB3 (XHCI) Host Controller is requesting an SMI.

30

0h

RO/V

ME SMI Status (ME_​SMI_​STS)

This bit will be set when ME is requesting an SMI#.

29

0h

RW/1C/V

Intel Serial I/O SMI Status (LPSS_​SMI_​STS)

This bit gets set when UART, I2C, or GSPI is requesting SMI #. This bit is set by hardware and cleared by software writing a 1 to this bit position

28

0h

RO/V

eSPI SMI Status (ESPI_​SMI_​STS)

This bit is set if an eSPI agent is requesting an SMI#. This bit is set by hardware and cleared by software writing a 1 to its bit position.

27

0h

RW/1C/V

GPIO Unlock SMI Status (GPIO_​UNLOCK_​SMI_​STS)

This bit will be set of the GPIO registers lockdown logic is requesting an SMI#. Writing a '1' to this bit position clears this bit to '0'.

26

0h

RO/V

SPI_​SMI Status (SPI_​SMI_​STS)

This bit will be set when the SPI logic is requesting an SMI#. This bit is read only because the sticky status and enable bits associated with this function are located in the SPI registers.

25

0h

RW/1C/V

SCC SMI Status (SDX_​SMI_​STS)

This bit gets set when SCC agent is requesting SMI#.This bit is set by hardware and cleared by software writing a 1 to this bit position

24:23

0h

RO

Reserved

22

0h

RO/V

INTERNAL_​TT Status (INTERNAL_​TT_​STS)

This bit will be set if the internal thermal throttle mechanism has changed state.

21

0h

RO/V

Monitor Status (MONITOR_​STS)

This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses).

20

0h

RO/V

PCI_​EXP_​SMI Status (PCI_​EXP_​SMI_​STS)

When set, a PCI Express SMI event occurred. This could be due to a PCI Express PME event or Hot Plug Event.

19

0h

RO/V

RTC Update-In-Progress SMI Status (RTC_​UIP_​SMI_​STS)

This bit will be set when the RTC Update-In-Progress signal transitions either from low-to-high or high-to-low, depending on the enables in the I/O Trap register space. This bit is Read Only. The sticky Read/Write Clear status bits are implemented in the I/O Trap register space. There is no need for a corresponding enable because individual enables are provided in the the I/O Trap register space.

18

0h

RW/1C/V

Thermal SMI Status (THERM_​SMI_​STS)

This bit will be set when the FW sets DRV_​THERM_​SMI_​SCI_​STS.DRV_​SMI_​STS bit. It is cleared by the Host Software

17

0h

RO/V

Legacy USB 2 Status (LEGACY_​USB2_​STS)

This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. All integrated USB2 Host Controllers are represented with this bit.

16

0h

RW/1C/V

SMBUS_​SMI Status (SMBUS_​SMI_​STS)

This bit is set to 1 to indicate that the SMI# was caused by:
1. The SMBus receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_​SMI_​EN bit is set and the SMBALERT_​DIS bit is cleared.
3. The SMBus receiving a HOST_​NOTIFY message and the HOST_​NOTIFY_​INTREN and the SMB_​SMI_​EN bits are set.
4. The SMBus receiving a SMI in S0 message.
This bit is sticky. It is cleared by writing a 1 to this bit position. Note that this bit is set from the 64 KHz clock domain used by the SMBus. Software must wait at least 15.63 microseconds

15:14

0h

RO

Reserved

13

0h

RW/1C/V

TCO Status (TCO_​STS)

1 = Indicates SMI was caused by the TCO logic. 0 = SMI not caused by TCO logic.

NOTE: Will not cause wake event. This bit is cleared by writing a 1 to this bit position.

12

0h

RO/V

DEVMON Status (DEVMON_​STS)

This read-only bit is set when bit 0 in the DEVTRAP_​STS register is set. It is not sticky, so writes to this bit will have no effect.

11

0h

RW/1C/V

MCSMI Status (MCSMI_​STS)

This bit is set if there is an access to the power management microcontroller range (62h or 66h). If this bit is set, and the MCSMI_​EN bit is also set, an SMI# is generated. This bit is set by hardware and cleared by software writing a 1 to its bit position.

10

0h

RO/V

GPIO SMI Status (GPIO_​SMI_​STS)

This bit will be a 1 if any GPIO that is enabled to trigger SMI is asserted. GPIOs that are not routed to cause an SMI will have no effect on this bit. This bit is NOT sticky. Writes to this bit will have no effect.

9

0h

RO/V

GPE0 Status (GPE0_​STS)

There are several status/enable bit pairs in GPE0_​STS/EN_​127_​96 that are capable of triggering SMIs. This bit is a logical OR of all of those pairs (i.e. this bit is asserted whenever at least one of those pairs has both the status and enable bit asserted). This bit is NOT sticky. Writes to this bit will have no effect. Note: The setting of this bit does not cause the SMI#.

The following bit pairs are included in this logical OR:

- GPE0_​STS/EN_​127_​96 [18, 17, 16, 13, 11, 10, 8, 2]

8

0h

RO/V

PM1 Status Register (PM1_​STS_​REG)

This is an OR of the bits (except for bits 5 and 4) in the ACPI PM1 Status Reg. (offset PMBASE+00h). Not sticky. Writes to this bit have no effect. Note: The setting of this bit does not cause the SMI#.

7

0h

RO

Reserved

6

0h

RW/1C/V

Software SMI Timer Status (SWSMI_​TMR_​STS)

This bit will be set to 1 by the hardware when the Software SMI# Timer expires. This bit will remain 1 until the software writes a 1 to this bit.

5

0h

RW/1C/V

APM Status (APM_​STS)

SMI# was generated by a write access to the APM control register and if the APMC_​EN bit is set. This bit is cleared by writing a one to its bit position.

4

0h

RW/1C/V

SMI_​ON_​SLP_​EN Status (SMI_​ON_​SLP_​EN_​STS)

This bit will be set when a write access attempts to set the SLP_​EN bit. This bit is cleared by writing a 1 to this bit position

3

0h

RO/V

Legacy USB Status (LEGACY_​USB_​STS)

This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB Legacy Keybd Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect.

2

0h

RW/1C/V

BIOS Status (BIOS_​STS)

This bit gets set by hardware when a 1 is written by software to the GBL_​RLS bit. When both BIOS_​EN and the BIOS_​STS bit are set, an SMI# will be generated. The BIOS_​STS bit is cleared when software writes a 1 to this bit position.

1:0

0h

RO

Reserved