31

1h

RW

ssCfgBlockPwrDwn4ActLFPS (SS_​CFG_​BLOCK_​PWRDWN_​4_​ACT_​LFPS)

Delay power down entry if Rx LFPS is active.
Setting this bit will block the controllers power down entry seq (for Sx/D3/D0i2 etc) if Rx LFPS is active. The power down entry will happen once a device stops sending LFPS.

30

1h

RW

dis_​clr_​ccs_​4hcreset (DIS_​CLR_​CCS_​4_​HCRESET)

Enable Clearing of CCS for HCReset -
Setting this bit clears the USB3 ports PORTSC.CCS bit upon HCReset.

29

0h

RW

disable_​rawlfps_​based_​wake_​fix (DISABLE_​RAWLFPS_​BASED_​WAKE_​FIX)

Disable Raw Lfps Detection Based Wake from P3
This bit is used to disable RTL fix provided to separate RawLFPS and RxElecIDle detection
0: Transition port to RESUME based on raw LFPS detection
1 : Transition port to RESUME based Filtered RxElecIdle detection

28

0h

RW

EXI OVERRIDE DISABLE (EXI_​OVERRIDE_​DIS)

EXI Override Disable

27:4

0h

RO

Rsvd (RSVD)

Reserved

3:0

0h

RW

SuperSpeed Port Enable Register (SSPE_​REG)

USB3 Port Enable
This field controls whether SuperSpeed capability is enabled for a given USB3 port.
When set to 1,
Enables SS termination
Enables PORTSC to to see the connects on the ports.
When set to 0,
Disables SS termination
Blocks PORTSC from reporting attach/connect.
Places port in the lowest power state.