Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795262 | 12/14/2023 | 001 | Public |
XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) – Offset 8174
XHC Latency Tolerance Parameters LTV Control
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31 | 0h | RW | Disable scheduler direct transition from IDLE to NO requirement (DIS_SDT_IDL_NR) 0: (default) allow scheduler direct transition from IDLE to NO requirement |
| 30 | 0h | RW | XHCI LTR Transition Policy (XLTRTP) (LTR_TRANS_POL) When 0, the LTR messaging state machine transitions through High Med Low Active states |
| 29 | 0h | RO | Reserved |
| 28 | 0h | RW | XHCI LTR Active Enable (XLTRAE) (XLTRAE) 0: The Power Scheduler will not request an LTR message on a transition to ACTIVE. |
| 27 | 0h | RW | Power Scheduler Local Clock Gating Enable (PWRLCGE) (PWRLCGE) 0: Power Scheduler does not use local clock gating |
| 26 | 0h | RW | LTR EVM Hysteresis Max Count (LTR_HYS_MAX) Power Scheduler's Periodic IDLE residency before we assert Periodic Complete |
| 25 | 0h | RW | Enable USB2 Port L0 LTV based on active async (EN_USB2_LTV_U0_PORT_ASYNC_ACTIVE) 0 - USB2 Port L0 LTV is used regardless of whether there is active async EPs being present or not (Legacy mode) |
| 24 | 1h | RW | XHCI LTR Enable (XLTRE) This bit must be set to enable LTV messaging from XHCI to the PMC. |
| 23:12 | 400h | RW | Periodic Active LTV (PA_LTV) 23:22 Latency Scale |
| 11:0 | c01h | RW | USB2 Port L0 LTV (USB2_PL0_LTV) 11:10 Latency Scale |