Host Enhanced Extend Register Status (HECI1_ENH_HERS) – Offset cbc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Host Enhanced Extend Register Status (HECI1_ENH_HERS) – Offset cbc

Bit Range	Default	Access	Field Name and Description
31	0h	RO/V	Extend Register Valid (ERV) Set by FW after all FW has been loaded and the measurement data has been stored in HERx registers. If ERA field is SHA-1, the result of the extend operation is in ENH_HER:5-1. If ERA field is SHA-256, the result is in ENH_HER:8-1. If ERA field is SHA-384, the result is in ENH_HER:12-1
30	1h	RO	Extend Feature Present (EFP) This bit is hardwired to 1 to allow driver software to easily detect the chipset supports the Extend Registers FW measurement feature.
29	0h	RO/V	Extend Complete (ERC) This bit is set by OCS hardware at the end of an extend operation if the EXTEND_OVER bit is set when setting the EXTEND_START bit. The ERC bit is cleared by HW whenever ROM writes/updates (to either 0 or 1) to the ERV bit when the ERV bit is unlocked. The ERV is unlocked when ERVL = 0.
28:20	0h	RO	Reserved (RSVD_28_20) Reserved.
19:16	0h	RO	Reserved
15:4	0h	RO	Reserved (RSVD_15_4) Reserved.
3:0	0h	RO/V	Extend Register Algorithm (ERA) This field indicates the hash algorithm used in the FW measurement Extend operation. Encodings are: 0x0: SHA-1 0x2: SHA-256 0x4: SHA-384 Other values: reserved. This field is set by FW with the used hash algorithm value when the ERV bit is set to 1. This field is meaningless when the ERV bit is 0. This field does NOT have any defined reset value.

Host Enhanced Extend Register DW1 (HECI1_ENH_HER1)

DEVIDLE Control (HECI1_DEVIDLEC) Host Enhanced Extend Register DW1 (HECI1_ENH_HER1)