Interrupt Status Register (IS) – Offset 8 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Interrupt Status Register (IS) – Offset 8

This register indicates which of the ports within the controller have an interrupt pending and require service.

Bit Range	Default	Access	Field Name and Description
31:8	0h	RO	RSVD0 (RSVD0) Reserved
7	0h	RW/1C/V	Interrupt Pending Status Port 7 (IPS7) If set, indicates that port 7 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 7 physically.
6	0h	RW/1C/V	Interrupt Pending Status Port 6 (IPS6) If set, indicates that port 6 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 6 physically.
5	0h	RW/1C/V	Interrupt Pending Status Port 5 (IPS5) If set, indicates that port 5 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 5 physically.
4	0h	RW/1C/V	Interrupt Pending Status Port 4 (IPS4) If set, indicates that port 4 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 4 physically.
3	0h	RW/1C/V	Interrupt Pending Status Port 3 (IPS3) If set, indicates that port 3 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 3 physically.
2	0h	RW/1C/V	Interrupt Pending Status Port 2 (IPS2) If set, indicates that port 2 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 2 physically.
1	0h	RW/1C/V	Interrupt Pending Status Port 1 (IPS1) If set, indicates that port 1 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 1 physically.
0	0h	RW/1C/V	Interrupt Pending Status Port 0 (IPS0) If set, indicates that port 0 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. This bit is only applicable to project(s) that has port 0 physically.

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