Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) – Offset f18 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) – Offset f18

This is the Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Margin Payload Status (MPSTS) This field is only meaningful, when the Margin Type This field must be reset to the default value if the Port goes to DL_Down status.
23	0h	RO	Reserved (RSVD_M) Reserved
22	0h	RO	Usage Model Status (UMS) This field must be reset to the default value if the Port goes to DL_Down status.
21:19	0h	RO	Margin Type Status (MTS) This field must be reset to the default value if the Port goes to DL_Down status.
18:16	0h	RO	Receiver Number Status (RNS) This field must be reset to the default value if the Port goes to DL_Down status.
15:8	0h	RO	Margin Payload (MP) This fields value is used in conjunction with the Margin Type field. The default value is 9Ch. This field must be reset to the default value if the Port goes to DL_Down status.
7	0h	RO	Reserved
6	0h	RO	Usage Model (UM) The default value is 0b. This field must be reset to the default value if the Port goes to DL_Down status.
5:3	0h	RO	Margin Type (MT) The default value is 111b. This field must be reset to the default value if the Port goes to DL_Down status.
2:0	0h	RO	Receiver Number (RN) The default value is 000b. This field must be reset to the default value if the Port goes to DL_Down status.

Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)

Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)