Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54

This register contains the power management data, control and status register bridge support extensions, control and status registers.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Data (DATA) Not implemented. Hardwired to 0.
23:16	0h	RO	Control/Status Register Bridge Support Extensions (CSRBSE) Not implemented. Hardwired to 0.
15	0h	RO	PME Status (PMESTS) Not implemented. Hardwired to 0.
14:13	0h	RO	Data Scale (DS) Not implemented. Hardwired to 0.
12:9	0h	RO	Data Select (DSEL) Not implemented. Hardwired to 0.
8	0h	RO	PME Enable (PMEEN) Not implemented. Hardwired to 0.
7:4	0h	RO	Reserved (RSVD1)
3	1h	RO	No Soft Reset (NSR) When set to 1, this bit indicates thatdevices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits.
2	0h	RO	Reserved (RSVD0)
1:0	0h	RW	Power State (PWRST) This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below: 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus; however, the data is discarded and no state change occurs.

P2SB PCI Configuration

Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID) P2SB PCI Configuration