THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG) – Offset 1010 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG) – Offset 1010

Bit Range	Default	Access	Field Name and Description
31:24	4h	RO	SPI WRITE Max Packet Size (SPI_WR_MPS) SPI Write Max Packet Size in 16 bytes. Software shall program this register after it negotiates with the device. This has to be programmed before it issues any other cycles to the device including the configuration, TX DMA and RX DMA.
23	0h	RW	Enable SPI Clock Divide by 8 to support low freq device. (SPI_LOW_FREQ_EN) 1: All the SPI read/write clock frequency (defined in SPI_TCWF/SPI_TCRF) will be divided further by 8 0: No further divider is supported.
22:20	7h	RW	SPI Touch Cycle Write Frequency (SPI_TCWF) The listed frequencies are approximate. 100 : 30MHz divide by 4 101 : 24MHz, divide by 5 110 : 20MHz, divide by 6 111 : 17MHz, divide by 7 Others: Reserved
19:18	0h	RW	SPI Touch IO Write mode (SPI_TWMODE) Firmware programs this mode after discovering capabilities of Touch device. 00 : Single IO Write (1-1-1 02h) enabled 01: Dual IO Write (1-2-2 B2h) enabled (DIOWE) (not supported by TGP/LKF, supported in ADP and later) 10: Quad IO Write (1-4-4/E2h) mode (QIOWE) (not supported by TGP/LKF, supported in ADP and later) 11: Quad Parallel IO Write (4-4-4/F2h) mode (QPIWE) (not supported)
17:16	0h	RO	Reserved (RSVD_17_16) Reserved.
15:7	4h	RW	SPI READ Max Packet Size (SPI_RD_MPS) SPI Read Max Packet Size in 16 bytes. Software shall program this register after it negotiates with the device. This has to be programmed before it issues any other cycles to the device including the configuration, TX DMA and RX DMA. For TGP/LKF, only 64B MPS is supported so this is a RO field and SW does not need to program it. For ADP,THC supports 64,128,256,512,1024,2048 and 4096B MPS.
6:4	7h	RW	SPI Touch Cycle Read Frequency (SPI_TCRF) The listed frequencies are approximate. 011 : 40MHz divide by 3 100 : 30MHz divide by 4 101 : 24MHz, divide by 5 110 : 20MHz, divide by 6 111 : 17MHz, divide by 7 Others: Reserved
3:2	0h	RW	SPI Touch IO Read mode (SPI_TRMODE) Firmware programs this mode after discovering capabilities of Touch device. 00 : Single IO Read (1-1-1 0B) enabled 01: Dual IO Read (1-2-2 BBh) enabled (DIORE) 10: Quad IO Read (1-4-4/EBh) mode (QIORE) 11: Quad Parrellel IO Read (4-4-4/FBh) mode (QPIRE) enabled (not supported)
1:0	3h	RW	SPI Touch IO Read Dummy Clocks (SPI_TRDC) Firmware programs this mode after discovering capabilities of Touch device. 00: 0 dummy byte (not supported) 01: 1 dummy byte (not supported) 10: 4 dummy bytes(not supported) 11: 8 dummy clocks