63:54

0h

RO

Reserved

53

0h

RO/V

RID-PRIV Supported (RPRIVS)

0: The hardware does not support RID-PRIV in scalable-mode context-entry.
1: The hardware supports RID-PRIV in scalable-mode context-entry.

52

1h

RO

Abort DMA Mode Support (ADMS)

0: The hardware does not support Abort DMA Mode.
1: The hardware supports Abort DMA Mode.

51

0h

RO/V

Performance Monitoring Support (PMS)

Refer to VT-d specification

50

0h

RO/V

TDX_​IO Support (TDXIO)

0: TDX IO not supported.
1: TDX IO supported.

49

1h

RO/V

RID_​PASID Support (RPS)

0: Hardware does not support RID_​PASID field in Scalablemode context-entry. It uses the value of 0 for RID_​PASID.
1: Hardware supports the RID_​PASID field in Scalable-mode context-entry.
Hardware implementations reporting Scalable Mode Translation Support (SMTS) as Clear also report this field as Clear.

48

0h

RO/V

Scalable Mode Page-walk Coherency (SMPWCS)

0: Hardware access to paging structures accessed through the PASID Table Entry are not snooped.
1: Hardware access to paging structures accessed through the PASID Table Entry are snooped if PWSNP field in the PASID Table Entry is Set. Paging structures accessed through the PASID Table Entry are not snooped if PWSNP field in the PASID Table Entry is Clear.
Hardware implementations reporting scalable Mode Translation Support (SMTS) as Clear, also report this field as Clear.

47

1h

RO/V

First-Level Translation Support (FLTS)

0: Hardware does not support PASID-Granular Translation Type of first-level (PGTT=001b) in Scalable-Mode PASID Table Entry.
1: Hardware supports PASID-Granular Translation Type of first-level (PGTT=001b) in Scalable-Mode PASID Table Entry.
Hardware implementations reporting Scalable Mode Translation Support (SMTS) as Clear also report this field as Clear.

46

1h

RO/V

Second-Level Translation Support (SLTS)

0: Hardware does not support PASID-Granular Translation Type of second-level (PGTT=010b) in Scalable-Mode PASID Table Entry.
1: Hardware supports PASID-Granular Translation Type of second-level (PGTT=010b) in Scalable-Mode PASID Table Entry.
Hardware implementations reporting Scalable Mode Translation Support (SMTS) as Clear also report this field as Clear.

45

0h

RO/V

Second-Level Accessed/Dirty Support (SLADS)

0: Hardware does not support Accessed/Dirty bits in Second-Level translation.
1: Hardware supports Accessed/Dirty bits in Second-Level translation.

44

0h

RO

Virtual Command Support (VCS)

0: Hardware does not support command submission to virtual-DMA Remapping hardware.
1: Hardware does support command submission to virtual-DMA Remapping hardware.
Hardware implementations of this architecture report a value of 0 in this field. Software implementations (emulation) of this architecture may report VCS=1. Software managing remapping hardware should be written to handle both values of VCS.

43

1h

RO/V

Scalable Mode Translation Support (SMTS)

0: Hardware does not support Scalable Mode DMA Remapping.
1: Hardware supports Scalable Mode DMA Remapping through scalable-mode context-table and PASID-table structures.
Hardware implementations reporting Queued Invalidation (QI) field as Clear also report this field as Clear.

42

0h

RO/V

Page Request Draining Support (PDS)

0: Hardware does not support Page-Request Drain (PD) flag in Inv_​wait_​dsc.
1: Hardware supports Page-Request Drain (PD) flag in Inv_​wait_​dsc.
This field is valid only when Device-TLB support field is reported as Set.

41

1h

RO/V

Device-TLB Invalidation Throttle (DIT)

0: Hardware does not support Device-TLB Invalidation Throttling.
1: Hardware supports Device-TLB Invalidation Throttling.
This field is valid only when Page Request Support (PRS) field is reported as Set.

40

0h

RO/V

Process Address Space ID Support (PASID)

0: Hardware does not support requests tagged with Process Address Space IDs.
1: Hardware supports requests tagged with Process Address Space IDs.

39:35

13h

RO/V

PASID Size Supported (PSS)

This field reports the PASID size supported by the remapping hardware for requests-with-PASID. A value of N in this field indicates hardware supports PASID field of N+1 bits (For example, value of 7 in this field, indicates 8-bit PASIDs are supported).
Requests-with-PASID with PASID value beyond the limit specified by this field are treated as error by the remapping hardware.
This field is valid only when PASID field is reported as Set.

34

0h

RO/V

Extended Accessed Flag Support (EAFS)

0: Hardware does not support the extended-accessed (EA) bit in first-level paging-structure entries.
1: Hardware supports the extended accessed (EA) bit in first-level paging-structure entries.
This field is valid only when PASID field is reported as Set.

33

1h

RO/V

No Write Flag Support (NWFS)

0: Hardware ignores the No Write (NW) flag in Device-TLB translationrequests, and behaves as if NW is always 0.
1: Hardware supports the No Write (NW) flag in Device-TLB translationrequests.
This field is valid only when Device-TLB support (DT) field is reported as Set.

32

0h

RO

Reserved

31

0h

RO/V

Supervisor Request Support (SRS)

0: H/W does not support requests-with-PASID seeking supervisor privilege.
1: H/W supports requests-with-PASID seeking supervisor privilege.
The field is valid only when PASID field is reported as Set.

30

0h

RO/V

Execute Request Support (ERS)

0: H/W does not support requests-with-PASID seeking execute permission.
1: H/W supports requests-with-PASID seeking execute permission.
This field is valid only when PASID field is reported as Set.

29

0h

RO/V

Page Request Support (PRS)

0: Hardware does not support Page Requests.
1: Hardware supports Page Requests
This field is valid only when Device-TLB (DT) field is reported as Set.

28:27

0h

RO

Reserved

26

1h

RO/V

Nested Translation Support (NEST)

0: Hardware does not support nested translations.
1: Hardware supports nested translations.
This field is valid only when PASID field is reported as Set.

25

0h

RO/V

Memory Type Support (MTS)

0: Hardware does not support Memory Type in first-level translation and Extended Memory type in second-level translation.
1: Hardware supports Memory Type in first-level translation and Extended Memory type in second-level translation.
This field is valid only when PASID and ECS fields are reported as Set.
Remapping hardware units with, one or more devices that operate in processor coherency domain, under its scope must report this field as Set.

24

0h

RO

Reserved

23:20

fh

RO/V

Maximum Handle Mask Value (MHMV)

The value in this field indicates the maximum supported value for the Handle Mask (HM) field in the interrupt entry cache invalidation descriptor (iec_​inv_​dsc).
This field is valid only when the IR field in Extended Capability register is reported as Set.

19:18

0h

RO

Reserved

17:8

efh

RO/V

IOTLB Register Offset (IRO)

This field specifies the offset to the IOTLB registers relative to the register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the address for the first IOTLB invalidation register is calculated as X+(16*Y).

7

1h

RO/V

Snoop Control (SC)

0: Hardware does not support 1-setting of the SNP field in the page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-table entries.

6

1h

RO/V

Pass Through (PT)

0: Hardware does not support pass-through translation type in context entries and extended-context-entries.
1: Hardware supports pass-through translation type in context entries and extended-context-entries.
Pass-through translation is specified through Translation-Type (T) field value of 10b in context-entries, or T field value of 010b in extended-context-entries.
Hardware implementations supporting PASID must report a value of 1b in this field.

5

0h

RO

Reserved

4

1h

RO/V

Extended Interrupt Mode (EIM)

0: On Intel64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode).
1: On Intel64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode).
This field is valid only on Intel64 platforms reporting Interrupt Remapping support (IR field Set).

3

1h

RO/V

Interrupt Remapping support (IR)

0: Hardware does not support interrupt remapping.
1: Hardware supports interrupt remapping.
Implementations reporting this field as Set must also support Queued Invalidation (QI).

2

1h

RO/V

Device-TLB Support (DT)

0: Hardware does not support device-IOTLBs.
1: Hardware supports Device-IOTLBs.
Implementations reporting this field as Set must also support Queued Invalidation (QI).
Hardware implementations supporting I/O Page Requests (PRS field Set in Extended Capability register) must report a value of 1b in this field.

1

1h

RO/V

Queued Invalidation Support (QI)

0: Hardware does not support queued invalidations.
1: Hardware supports queued invalidations.

0

0h

RO/V

Page-Walk Coherency (C)

This field indicates if hardware access to the root, context, extended-context and interrupt-remap tables, and second-level paging structures for requests-without-PASID, are coherent (snooped) or not.
0: Indicates hardware accesses to remapping structures are non-coherent.
1: Indicates hardware accesses to remapping structures are coherent.
Hardware access to advanced fault log, invalidation queue, invalidation semaphore, page-request queue, PASID-table, PASID-state table, and first-level page-tables are always coherent.