Intel® Core™ Ultra Processors for H-series and U-series Platforms CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795258 | 07/29/2024 | Public |
MemSS PMA init state register (MEMSS_PMA_CR_INIT_STATE) – Offset 13d0c
This register is used as interface between MRC and MemSS PMA during memory initialization and training by MRC to communicate save or MRC done indication to MemSS PMA. Register must be locked after MRC_DONE.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:6 | 0h | RO | Reserved |
| 5 | 0h | RO/V | Memory Configuration Done Acknowledgement (MEM_CONFIG_DONE_ACK) Mem Config Done Ack from MemSS PMA to MRC. |
| 4 | 0h | RW | Memory Configuration Done (MEM_CONFIG_DONE) BIOS sets the bit to indicate that all the memory configuration is complet to MemSS PMA. |
| 3 | 0h | RW/V | MRC GV3 Save Request (MRC_SAVE3) MRC requests to save GV3 by setting the bit. MemSS PMA acknowledges by clearing the bit after save operation is complete. |
| 2 | 0h | RW/V | MRC GV2 Save Request (MRC_SAVE2) MRC requests to save GV2 by setting the bit. MemSS PMA acknowledges by clearing the bit after save operation is complete. |
| 1 | 0h | RW/V | MRC GV1 Save Request (MRC_SAVE1) MRC requests to save GV1 by setting the bit. MemSS PMA acknowledges by clearing the bit after save operation is complete. |
| 0 | 0h | RW/V | MRC GV0 Save Request (MRC_SAVE0) MRC requests to save GV0 by setting the bit. MemSS PMA acknowledges by clearing the bit after save operation is complete. |