PCI Command & Status Register (PCICMD_STS) – Offset 4 - 001 - ID:795260 | Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

ID	Date	Version	Classification
795260	12/14/2023	001	Public

PCI Command & Status Register (PCICMD_STS) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0h	RW/V	Detected Parity Error (DPE) [BR]0 = No parity error detected.[BR] 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.
30	0h	RW/V	Signaled System Error (SSE) [BR]0 = No system error signaled.[BR] 1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.
29	0h	RW/V	Received Master Abort (RMA) [BR]0 = Root port has not received a completion with unsupported request status from the backbone.[BR] 1 = Set when the GbE LAN controller receives a completion with unsupported request status from the backbone.
28	0h	RW/V	Received Target Abort (RTA) [BR]0 = Root port has not received a completion with completer abort from the backbone.[BR] 1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone.
27	0h	RW/V	Signaled Target Abort (STA) [BR]0 = No target abort received.[BR] 1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream device onto the backbone.
26:25	0h	RW/V	DEVSEL# Timing Status (DEV_STS) Hardwired to 0.
24	0h	RW/V	Master Data Parity Error Detected (DPED) [BR]0 = No data parity error received.[BR] 1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone and PCIMD.PER (D25:F0, bit 6) is set.
23	0h	RW/V	Fast Back to Back Capable (FB2BC) Hardwired to 0.
22	0h	RO	Reserved
21	0h	RW/V	66 MHz Capable (MHZ_66_CPBL) Hardwired to 0.
20	1h	RW/V	Capabilities List (NEW_CPBL) Hardwired to 1. Indicates the presence of a capabilities list.
19	0h	RW/V	Interrupt Status (INT_STAT) Indicates status of hot-plug and power management interrupts on the root port that result in INTx# message generation.[BR] 0 = Interrupt is de-asserted.[BR] 1 = Interrupt is asserted.[BR] This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).
18:11	0h	RO	Reserved
10	0h	RW	Interrupt Disable (INT_DIS) This disables pin-based INTx# interrupts on enabled hot-plug and power management events. This bit has no effect on MSI operation.[BR] 0 = Internal INTx# messages are generated if there is an interrupt for hot-plug or power management and MSI is not enabled.[BR] 1 = Internal INTx# messages will not be generated.[BR] This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and de-assert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set.
9	0h	RW/V	Fast Back to Back Enable (FBE) Hardwired to 0.
8	0h	RW	SERR# Enable (SEE) [BR]0 = Disable[BR] 1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is set.
7	0h	RW/V	Wait Cycle Control (WCC) Hardwired to 0.
6	0h	RW	Parity Error Response (PER) [BR]0 = Disable.[BR] 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.
5	0h	RW/V	Palette Snoop Enable (PSE) Hardwired to 0.
4	0h	RW/V	Postable Memory Write Enable (PMWE) Hardwired to 0.
3	0h	RW/V	Special Cycle Enable (SCE) Hardwired to 0.
2	0h	RW	Bus Master Enable (BME) [BR]0 = Disable. All cycles from the device are master aborted[BR] 1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN device.
1	0h	RW	Memory Space Enable (MSE) [BR] 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone.[BR] 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the Gigabit LAN device.
0	0h	RW/V	I/O Space Enable (IOSE) This bit controls access to the I/O space registers.[BR] 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone.[BR] 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the Gigabit LAN device.