Control Register High 1 (CTL_HI1) – Offset 874 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
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GSPI PCI Configuration
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I3C / I2C / UART / GSPI PCR
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I3C DMA
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I3C PCI Configuration
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Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
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Intergrated GbE MMIO
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PMC PCI Configuration
PMC SSRAM PCI Configuration
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SATA ABAR
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA PCI Configuration
SATA Port 0 ABAR
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SATA Port 2 ABAR
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SATA Port 4 ABAR
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SATA Port 7 ABAR
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SPI MMIO
SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Control Register High 1 (CTL_HI1) – Offset 874

Same description as CTL_HI0

Bit Range	Default	Access	Field Name and Description
31:29	0h	RW	CH_CLASS (CH_CLASS) Channel Class. A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. This field must be programmed within 0 to (N_CHNLS-1). A programmed value outside this range will cause erroneous behavior.
28:18	0h	NA	RESERVED (RESERVED0) Reserved
17	0h	RW	DONE (DONE) If status write-back is enabled, the upper word of the control register, CTL_HIn, is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTL_HI.DONE bit to see when a block transfer is complete. The LLI CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is not cleared.
16:0	0h	RW	BLOCK_TS (BLOCK_TS) Block Transfer Size (in Bytes). Since the DMA is always the flow controller, the user needs to write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of bytes to transfer for every block transfer. Once the transfer starts (i.e. channel is enabled), the read-back value is the total number of bytes for which Read Commands have already been sent to the source. It doesnt mean Bytes that are already in the FIFO. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

Source Status 1 (SSTAT1)

Control Register Low 1 (CTL_LO1) Source Status 1 (SSTAT1)