eSPI Device Configuration Register and Link Control (SLV_CFG_REG_CTL) – Offset 4000 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

eSPI Device Configuration Register and Link Control (SLV_CFG_REG_CTL) – Offset 4000

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1S/V	Device Configuration Register Access Enable (SCRE) Writing a 1 to this field triggers an access (SCRT) to a Device Config Register ('Go'). Hardware clears this bit to 0 (& sets the SCRS field) when the transaction has completed on the eSPI bus. In the case of a configuration/status register read, the data is valid only after this bit has been cleared by HW. The SCRE is effective only if SCRS is clear.
30:28	0h	RW/1C/V	Device Configuration Register Access Status (SCRS) This field is set by upon the completion of a configuration register access (SCRE). Software must clear this field by writing all 1s before initiating another device configuration register access (SCRE). 3'h0: Status not valid 3'h1: Device No_Response 3'h2: Device Response CRC Error 3'h3: Device Response Fatal Error 3'h4: Device Response Non-Fatal Error 3'h5 3'h6: Reserved 3'h7: No errors (transaction completed successfully)
27	0h	RW/1S	IOSF-SB eSPI Link Configuration Lock (SBLCL) When set, eSPI-MC prevents writes (i.e., SET_CONFIGURATION) from this IOSF-SB TASC mechanism to any eSPI Specification defined Device Capabilities and Configuration registers in the reserved register address range (0h 7FFh). Access to device implementation specific configuration registers outside this range are not impacted by this lock bit and are always available access protections to such registers are device implementation dependent. This bit cannot be written to 0 once it has been set to 1. It can only be cleared by PLTRST# assertion. The lock is automatically disabled if and while the LNKERR_SLV0.SLCRR register bit is asserted (upon an eSPI link Fatal Error condition) to allow BIOS (or another SW agent) to attempt to recover the link. [b]Note:[/b] This bit has no effect (i.e., IOSF-SB TASC is always enabled) when PLTRST# is asserted. [b]BIOS Note:[/b] BIOS must ensure that this bit is set to 1 after initial eSPI link configuration is over to prevent any further (unintentional or malicious) changes to the eSPI link configuration via IOSF-SB (per AR from eSPI SAFE S1 review).
26:21	0h	RO	Reserved (RSVD) Reserved
20:19	0h	RW	Target Device ID (SID) eSPI Device ID (CS#) to which the Device Configuration Register Access (SCRT) is directed. 2'b00: eSPI Device 0 (EC/BMC) 2'b01: eSPI Device 1 (Note: Only supported when a when a second eSPI device is present) 2'b10: eSPI Device 2 (Note: Only supported when a when a third eSPI device is present) 2'b11: eSPI Device 3 (Note: Only supported when a when a fourth eSPI device is present)
18	0h	RO	Reserved 1 (RSVD1) Reserved
17:16	0h	RW	Device Configuration Register Access Type (SCRT) Rd/Wr/Status 2'b00: Device Configuration register read from address SCRA[11:0] (GET_CONFIG) 2'b01: Device Configuration register write to address SCRA[11:0] (SET_CONFIG) 2'b10: Device Status register read (GET_STATUS) 2'b11: In-Band Reset Writes to Device Configuration registers in the reserved address range (0h 7FFh) are gated by the SBLCL bit. Setting this field to 2'b10 triggers a Get_Status command to the device. In this case, the SCRA field is ignored and only the lower 16-bits of the returned data (SLV_CFG_REG_DATA[15:0]) are valid. Setting this field to 2'b11 triggers an In-Band Reset command to the device. In this case, the SCRA field is ignored and no data is returned. This command resets the link for the targeted device to a default configuration. Software is responsible for reinitializing the link to optimized (higher performance) settings using these registers.
15:12	0h	RO	Reserved 2 (RSVD2) Reserved
11:0	0h	RW	Device Configuration Register Address (SCRA)