PCI Command & Status Register (DMI_CONFIG1) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

PCI Command & Status Register (DMI_CONFIG1) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0h	RW/V	Detected Parity Error (DET_PTY_ERR) 0 = No parity error detected. 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.
30	0h	RW/V	Signaled System Error (SIG_SYS_ERR) 0 = No system error signaled. 1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.
29	0h	RW/V	Received Master Abort (RCD_MST_ABT) 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the GbE LAN controller receives a completion with unsupported request status from the backbone.
28	0h	RW/V	Received Target Abort (RCD_TGT_ABT) 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone.
27	0h	RW/V	Signaled Target Abort (SIG_TGT_ABT) 0 = No target abort received. 1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream device onto the backbone.
26:25	0h	RW/V	DEVSEL# Timing Status (DEVSEL_TIMG) Hardwired to 0.
24	0h	RW/V	Master Data Parity Error Detected (DATA_PTY_RPTD) 0 = No data parity error received. 1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone and PCIMD.PER (D25:F0, bit 6) is set.
23	0h	RW/V	Fast Back to Back Capable (FAST_B2B_CPBL) Hardwired to 0.
22	0h	RW/V	Reserved (Reserved22)
21	0h	RW/V	66 MHz Capable (MHZ_66_CPBL) Hardwired to 0.
20	1h	RW/V	Capabilities List (NEW_CPBL) Hardwired to 1. Indicates the presence of a capabilities list.
19	0h	RW/V	Interrupt Status (INT_STAT) Indicates status of hot-plug and power management interrupts on the root port that result in INTx# message generation. 0 = Interrupt is de-asserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).
18:11	0h	RW/V	Reserved (Reserved_18)
10	0h	RW	Interrupt Disable (INT_DIS) This disables pin-based INTx# interrupts on enabled hot-plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for hot-plug or power management and MSI is not enabled. 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and de-assert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set.
9	0h	RW/V	Fast Back to Back Enable (FAST_B2B_EN) Hardwired to 0.
8	0h	RW	SERR# Enable (SERR_NUM_EN) 0 = Disable 1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is set.
7	0h	RW/V	Wait Cycle Control (WAIT_CYC_EN) Hardwired to 0.
6	0h	RW	Parity Error Response (PARITY_ERR_RSP) 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.
5	0h	RW/V	Palette Snoop Enable (PALET_SNP_EN) Hardwired to 0.
4	0h	RW/V	Postable Memory Write Enable (MWI_EN) Hardwired to 0.
3	0h	RW/V	Special Cycle Enable (SP_CYCLE_MON) Hardwired to 0.
2	0h	RW	Bus Master Enable (EN_MASTERING) 0 = Disable. All cycles from the device are master aborted 1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN device.
1	0h	RW	Memory Space Enable (MEM_ACCESS_EN) 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the Gigabit LAN device.
0	0h	RW/V	I/O Space Enable (IO_ACCESS_EN) This bit controls access to the I/O space registers. 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the Gigabit LAN device.