Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) – Offset 10ec - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) – Offset 10ec

Bit Range	Default	Access	Field Name and Description
31:16	2h	RW/L	Value of Interrupt Type Touch Data (THC_M_PRT_INTTYP_DATA_VAL) This is a bit mask where SW can set one or multiple bits in this field for THC HW to decode the 'interrupt type' field as the 'read_data_available' interrupt, which will be handled by the HW DMA instead of directly interrupting SW as NDDI. Default to 0x0002 for the THC mode (e.g. value 1 = touch data ready, thus bit 1 is set to 1). For HID SPI mode, driver may need to set multiple bits in this field to support multiple interrupt type with RXDMA.
15	0h	RW	Enable bit to send Interrupt Cause Register (THC_M_PRT_SEND_ICR_US_EN) When this bit is 1 and INT_SW_DMA_EN=0, in RXDMA mode, THC will send the touch device Interrupt Cause Register value of the first uFrame in every frame as the first DW in the corresponding PRD table.
14:10	1eh	RW/L	Bit Offset of End of Frame (THC_M_PRT_EOF_OFFSET) Touch device's 'End of Frame' field's starting bit position in the 'interrupt cause register'. Default to 0x1E(30) for the THC mode. Set to 0x8 for the HIDSPI protocol where the 'Last Segment' starts from bit 8.
9:5	4h	RW/L	Length of Interrupt Type (THC_M_PRT_INTTYP_LEN) Touch device's 'interrupt Type' field's length in the 'interrupt cause register'. Default to 4 for the THC mode and HIDSPI mode.
4:0	0h	RW/L	Bit Offset of Interrupt Type (THC_M_PRT_INTTYP_OFFSET) Touch device's 'interrupt Type' fields starting bit position in the interrupt cause register. Default to 0 for the THC mode. Set to 0x4 for the HIDSPI protocol where the 'Input Report Type' starts from bit 4.

Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2)

THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT) Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2)