Intel® Core™ Ultra 200S and 200HX Series Processors CFG & MEM Registers

ID Date Version Classification
835538 01/29/2025 001 Public
Document Table of Contents
Document Table of Contents
Introduction Processor Configuration Register Definitions and Address Ranges D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1) D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2) D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1) D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5) D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2) D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR D10:F0 Platform Monitoring Technology (PMT) Registers D11:F0 Vision Processing Unit D14:F0 Volume Management Device D14:F0 Volume Management Device MEMBAR2 D2:F0 Processor Graphics D4:F0 Dynamic Tuning Technology
Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1) Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_PCU) Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_PCU) P-State Limits (P_STATE_LIMITS_0_2_0_GTTMMADR) Plane Turbo Performance BIAS (GT_IA_PERF_BIAS_0_2_0_GTTMMADR) Secondare Plane Turbo Power Policy (SECP_TURBO_PLCY_0_2_0_GTTMMADR)
Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_PCU)
Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_PCU)
P-State Limits (P_STATE_LIMITS_0_2_0_GTTMMADR)
Plane Turbo Performance BIAS (GT_IA_PERF_BIAS_0_2_0_GTTMMADR)
Secondare Plane Turbo Power Policy (SECP_TURBO_PLCY_0_2_0_GTTMMADR)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2) (RP_STATE_CAP_0_0_0_PCU) Ratio Sum of Active GT (PKG_GCD_C0_ANY_RATIO_0_2_0_GTTMMADR) Package GCD C0 EUs SUM (PKG_GCD_C0_EUS_SUM_0_2_0_GTTMMADR) Cycle Sum of Any Active Media (PKG_MEDIA_C0_ANY_SLICE_0_2_0_GTTMMADR) Cycle Sum of All Active Media (PKG_MEDIA_C0_SLICES_SUM_0_2_0_GTTMMADR) Ratio Sum of Active Media (PKG_MEDIA_C0_ANY_RATIO_0_2_0_GTTMMADR) Ratio Sum of Active Media Slice (PKG_MEDIA_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR) Package Media C0 EUs SUM (PKG_MEDIA_C0_EUS_SUM_0_2_0_GTTMMADR) Ratio Sum of Active GCD Slice (PKG_GCD_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR) Cycle Sum of Active Media (PKG_MEDIA_C0_ANY_0_2_0_GTTMMADR) Cycle Sum of Active Graphics (PKG_GCD_C0_ANY_0_2_0_GTTMMADR) Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_2_0_GTTMMADR) Cycle Sum of Any Active GT Slice (PKG_GCD_C0_ANY_SLICE_0_2_0_GTTMMADR) Cycle Sum of All Active GT Slice (PKG_GCD_C0_SLICES_SUM_0_2_0_GTTMMADR) Thermal Status GT (THERM_STATUS_GT_0_2_0_GTTMMADR) GT Thermal Interrupt (THERM_INTERRUPT_GT_0_2_0_GTTMMADR) PCU Reference Clock (PCU_REFERENCE_CLOCK_0_2_0_GTTMMADR)
(RP_STATE_CAP_0_0_0_PCU)
Ratio Sum of Active GT (PKG_GCD_C0_ANY_RATIO_0_2_0_GTTMMADR)
Package GCD C0 EUs SUM (PKG_GCD_C0_EUS_SUM_0_2_0_GTTMMADR)
Cycle Sum of Any Active Media (PKG_MEDIA_C0_ANY_SLICE_0_2_0_GTTMMADR)
Cycle Sum of All Active Media (PKG_MEDIA_C0_SLICES_SUM_0_2_0_GTTMMADR)
Ratio Sum of Active Media (PKG_MEDIA_C0_ANY_RATIO_0_2_0_GTTMMADR)
Ratio Sum of Active Media Slice (PKG_MEDIA_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR)
Package Media C0 EUs SUM (PKG_MEDIA_C0_EUS_SUM_0_2_0_GTTMMADR)
Ratio Sum of Active GCD Slice (PKG_GCD_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR)
Cycle Sum of Active Media (PKG_MEDIA_C0_ANY_0_2_0_GTTMMADR)
Cycle Sum of Active Graphics (PKG_GCD_C0_ANY_0_2_0_GTTMMADR)
Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_2_0_GTTMMADR)
Cycle Sum of Any Active GT Slice (PKG_GCD_C0_ANY_SLICE_0_2_0_GTTMMADR)
Cycle Sum of All Active GT Slice (PKG_GCD_C0_SLICES_SUM_0_2_0_GTTMMADR)
Thermal Status GT (THERM_STATUS_GT_0_2_0_GTTMMADR)
GT Thermal Interrupt (THERM_INTERRUPT_GT_0_2_0_GTTMMADR)
PCU Reference Clock (PCU_REFERENCE_CLOCK_0_2_0_GTTMMADR)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1) Vendor ID (VID_0_0_0_PCI) Device ID (DID_0_0_0_PCI) PCI Command (PCICMD_0_0_0_PCI) PCI Status (PCISTS_0_0_0_PCI) Revision ID (RID_0_0_0_PCI) Class Code Programming Interface (CC_PI_0_0_0_PCI) Basic Class Code (CC_BCC_0_0_0_PCI) Header Type (HDR_0_0_0_PCI) Subsystem Vendor Identification (SVID_0_0_0_PCI) Subsystem Identification (SID_0_0_0_PCI) Capabilities Pointer (CAPPTR_0_0_0_PCI)
Vendor ID (VID_0_0_0_PCI)
Device ID (DID_0_0_0_PCI)
PCI Command (PCICMD_0_0_0_PCI)
PCI Status (PCISTS_0_0_0_PCI)
Revision ID (RID_0_0_0_PCI)
Class Code Programming Interface (CC_PI_0_0_0_PCI)
Basic Class Code (CC_BCC_0_0_0_PCI)
Header Type (HDR_0_0_0_PCI)
Subsystem Vendor Identification (SVID_0_0_0_PCI)
Subsystem Identification (SID_0_0_0_PCI)
Capabilities Pointer (CAPPTR_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2) MCHBAR Base Address Register (MCHBAR_0_0_0_PCI) Graphics Control (GGC_0_0_0_PCI) Device Enable (DEVEN_0_0_0_PCI) Protected Audio Video Path Control (PAVPC_0_0_0_PCI) DMA Protected Range (DPR_0_0_0_PCI) PCIEXBAR Base Address Register (PCIEXBAR_0_0_0_PCI) DMIBAR Base Address Register (DMIBAR_0_0_0_PCI) Programmable Attribute Map 0 (PAM0_0_0_0_PCI) Programmable Attribute Map 1 (PAM1_0_0_0_PCI) Programmable Attribute Map 2 (PAM2_0_0_0_PCI) Programmable Attribute Map 3 (PAM3_0_0_0_PCI) Programmable Attribute Map 4 (PAM4_0_0_0_PCI) Programmable Attribute Map 5 (PAM5_0_0_0_PCI) Programmable Attribute Map 6 (PAM6_0_0_0_PCI) Legacy Access Control (LAC_0_0_0_PCI) Top of Memory (TOM_0_0_0_PCI) Top of Upper Usable DRAM (TOUUD_0_0_0_PCI) Base Data of Stolen Memory (BDSM_0_0_0_PCI) Base of GTT Stolen Memory (BGSM_0_0_0_PCI) TSEG Memory Base (TSEGMB_0_0_0_PCI) Top of Low Usable DRAM (TOLUD_0_0_0_PCI) Scratchpad Data (SKPD_0_0_0_PCI) Capabilities A (CAPID0_A_0_0_0_PCI) Capabilities B (CAPID0_B_0_0_0_PCI) Capabilities C (CAPID0_C_0_0_0_PCI) Capabilities E (CAPID0_E_0_0_0_PCI)
MCHBAR Base Address Register (MCHBAR_0_0_0_PCI)
Graphics Control (GGC_0_0_0_PCI)
Device Enable (DEVEN_0_0_0_PCI)
Protected Audio Video Path Control (PAVPC_0_0_0_PCI)
DMA Protected Range (DPR_0_0_0_PCI)
PCIEXBAR Base Address Register (PCIEXBAR_0_0_0_PCI)
DMIBAR Base Address Register (DMIBAR_0_0_0_PCI)
Programmable Attribute Map 0 (PAM0_0_0_0_PCI)
Programmable Attribute Map 1 (PAM1_0_0_0_PCI)
Programmable Attribute Map 2 (PAM2_0_0_0_PCI)
Programmable Attribute Map 3 (PAM3_0_0_0_PCI)
Programmable Attribute Map 4 (PAM4_0_0_0_PCI)
Programmable Attribute Map 5 (PAM5_0_0_0_PCI)
Programmable Attribute Map 6 (PAM6_0_0_0_PCI)
Legacy Access Control (LAC_0_0_0_PCI)
Top of Memory (TOM_0_0_0_PCI)
Top of Upper Usable DRAM (TOUUD_0_0_0_PCI)
Base Data of Stolen Memory (BDSM_0_0_0_PCI)
Base of GTT Stolen Memory (BGSM_0_0_0_PCI)
TSEG Memory Base (TSEGMB_0_0_0_PCI)
Top of Low Usable DRAM (TOLUD_0_0_0_PCI)
Scratchpad Data (SKPD_0_0_0_PCI)
Capabilities A (CAPID0_A_0_0_0_PCI)
Capabilities B (CAPID0_B_0_0_0_PCI)
Capabilities C (CAPID0_C_0_0_0_PCI)
Capabilities E (CAPID0_E_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1) VT IOMMU VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
VT IOMMU VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2) Type-C Sub-system Device Enable (TCSS_DEVEN_0_0_0_MCHBAR_IMPH) Capabilities D (CAPID0_D_0_0_0_MCHBAR) Capabilities F (CAPID0_F_0_0_0_PCI) SOUTH_IOE_DECODE MCHBAR_IMPH (SOUTH_IOE_DECODE_0_0_0_MCHBAR_IMPH)
Type-C Sub-system Device Enable (TCSS_DEVEN_0_0_0_MCHBAR_IMPH)
Capabilities D (CAPID0_D_0_0_0_MCHBAR)
Capabilities F (CAPID0_F_0_0_0_PCI)
SOUTH_IOE_DECODE MCHBAR_IMPH (SOUTH_IOE_DECODE_0_0_0_MCHBAR_IMPH)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1) In-Band ECC Activate (IBECC_ACTIVATE) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_0) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_1) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_2) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_3) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_4) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_5) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_6) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_7) ECC Protected VC0 Read Data Request Count (ECC_VC0_RD_REQCOUNT) ECC Protected VC1 Read Data Request Count (ECC_VC1_RD_REQCOUNT) ECC Protected VC0 Write Data Request Count (ECC_VC0_WR_REQCOUNT) ECC Protected VC1 Write Data Request Count (ECC_VC1_WR_REQCOUNT) Unprotected VC0 Read Request Count (NOECC_VC0_RD_REQCOUNT) Unprotected VC1 Read Request Count (NOECC_VC1_RD_REQCOUNT) Unprotected VC0 Write Request Count (NOECC_VC0_WR_REQCOUNT) Unprotected VC1 Write Request Count (NOECC_VC1_WR_REQCOUNT) ECC Error Log (ECC_ERROR_LOG) Parity Error Log (PARITY_ERR_LOG) ECC Injection Address Mask (ECC_INJ_ADDR_MASK) ECC Error Injection Address Base (ECC_INJ_ADDR_BASE) Parity Error Injection (PARITY_ERR_INJ) IBECC ECC Error Injection Control (ECC_INJ_CONTROL) Request Counter (ECC_VC0_SYND_RD_REQCOUNT) Request Counter (ECC_VC1_SYND_RD_REQCOUNT) Request Counter (ECC_VC0_SYND_WR_REQCOUNT) Request Counter (ECC_VC1_SYND_WR_REQCOUNT) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_0) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_1) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_2) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_3) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_4) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_5) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_6) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_7) ECC Error Counter (ECC_ERR_COUNT) IBECC Memory Initialization Control (IBECC_MEMORY_INIT_CONTROL)
In-Band ECC Activate (IBECC_ACTIVATE)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_0)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_1)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_2)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_3)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_4)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_5)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_6)
IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_7)
ECC Protected VC0 Read Data Request Count (ECC_VC0_RD_REQCOUNT)
ECC Protected VC1 Read Data Request Count (ECC_VC1_RD_REQCOUNT)
ECC Protected VC0 Write Data Request Count (ECC_VC0_WR_REQCOUNT)
ECC Protected VC1 Write Data Request Count (ECC_VC1_WR_REQCOUNT)
Unprotected VC0 Read Request Count (NOECC_VC0_RD_REQCOUNT)
Unprotected VC1 Read Request Count (NOECC_VC1_RD_REQCOUNT)
Unprotected VC0 Write Request Count (NOECC_VC0_WR_REQCOUNT)
Unprotected VC1 Write Request Count (NOECC_VC1_WR_REQCOUNT)
ECC Error Log (ECC_ERROR_LOG)
Parity Error Log (PARITY_ERR_LOG)
ECC Injection Address Mask (ECC_INJ_ADDR_MASK)
ECC Error Injection Address Base (ECC_INJ_ADDR_BASE)
Parity Error Injection (PARITY_ERR_INJ)
IBECC ECC Error Injection Control (ECC_INJ_CONTROL)
Request Counter (ECC_VC0_SYND_RD_REQCOUNT)
Request Counter (ECC_VC1_SYND_RD_REQCOUNT)
Request Counter (ECC_VC0_SYND_WR_REQCOUNT)
Request Counter (ECC_VC1_SYND_WR_REQCOUNT)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_0)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_1)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_2)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_3)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_4)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_5)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_6)
ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_7)
ECC Error Counter (ECC_ERR_COUNT)
IBECC Memory Initialization Control (IBECC_MEMORY_INIT_CONTROL)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2) Inter-Channel Decode Parameters (MAD_INTER_CHANNEL_0_0_0_MCHBAR) Intra-Channel 0 Decode Parameters (MAD_INTRA_CH0_0_0_0_MCHBAR) Intra-Channel 1 Decode Parameters (MAD_INTRA_CH1_0_0_0_MCHBAR) Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR) Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR) Opportunistic self refresh idle timer register (PM_OPP_SREF_IDLE_TIMER_0_0_0_MCHBAR) Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR) Read Occupancy Count (READ_OCCUPANCY_COUNT_0_0_0_MCHBAR) Address Compare for ECC Error Inject (ECC_Inj_Addr_Compare_0_0_0_MCHBAR) Remap Base (REMAPBASE_0_0_0_MCHBAR) Remap Limit (REMAPLIMIT_0_0_0_MCHBAR) WrCAS Counter (PWM_WRCAS_COUNT_0_0_0_MCHBAR) PWM NON SR COUNT 0 0 0 MCHBAR (PWM_NON_SR_COUNT_0_0_0_MCHBAR) PWM ACT COUNT 0 0 0 MCHBAR (PWM_ACT_COUNT_0_0_0_MCHBAR) Address Mask for ECC Error Inject (ECC_Inj_Addr_Mask_0_0_0_MCHBAR) PMON GLOBAL CONTROL 0 0 0 MCHBAR (PMON_GLOBAL_CONTROL_0_0_0_MCHBAR) PMON UNIT CONTROL 0 0 0 MCHBAR (PMON_UNIT_CONTROL_0_0_0_MCHBAR) PMON GLOBAL STATUS 0 0 0 MCHBAR (PMON_GLOBAL_STATUS_0_0_0_MCHBAR) PMON UNIT STATUS 0 0 0 MCHBAR (PMON_UNIT_STATUS_0_0_0_MCHBAR) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR[0]) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR[0]) OS Telemetry Control (OS_TELEMETRY_CONTROL_0_0_0_MCHBAR)
Inter-Channel Decode Parameters (MAD_INTER_CHANNEL_0_0_0_MCHBAR)
Intra-Channel 0 Decode Parameters (MAD_INTRA_CH0_0_0_0_MCHBAR)
Intra-Channel 1 Decode Parameters (MAD_INTRA_CH1_0_0_0_MCHBAR)
Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR)
Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR)
Opportunistic self refresh idle timer register (PM_OPP_SREF_IDLE_TIMER_0_0_0_MCHBAR)
Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR)
RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)
Read Occupancy Count (READ_OCCUPANCY_COUNT_0_0_0_MCHBAR)
Address Compare for ECC Error Inject (ECC_Inj_Addr_Compare_0_0_0_MCHBAR)
Remap Base (REMAPBASE_0_0_0_MCHBAR)
Remap Limit (REMAPLIMIT_0_0_0_MCHBAR)
WrCAS Counter (PWM_WRCAS_COUNT_0_0_0_MCHBAR)
PWM NON SR COUNT 0 0 0 MCHBAR (PWM_NON_SR_COUNT_0_0_0_MCHBAR)
PWM ACT COUNT 0 0 0 MCHBAR (PWM_ACT_COUNT_0_0_0_MCHBAR)
Address Mask for ECC Error Inject (ECC_Inj_Addr_Mask_0_0_0_MCHBAR)
PMON GLOBAL CONTROL 0 0 0 MCHBAR (PMON_GLOBAL_CONTROL_0_0_0_MCHBAR)
PMON UNIT CONTROL 0 0 0 MCHBAR (PMON_UNIT_CONTROL_0_0_0_MCHBAR)
PMON GLOBAL STATUS 0 0 0 MCHBAR (PMON_GLOBAL_STATUS_0_0_0_MCHBAR)
PMON UNIT STATUS 0 0 0 MCHBAR (PMON_UNIT_STATUS_0_0_0_MCHBAR)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR[0])
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR[0])
OS Telemetry Control (OS_TELEMETRY_CONTROL_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3) PRE Command Timing (TC_PRE_0_0_0_MCHBAR) RD to RD Timings (TC_RDRD_0_0_0_MCHBAR) RD to WR Timings (TC_RDWR_0_0_0_MCHBAR) WR to RD Timings (TC_WRRD_0_0_0_MCHBAR) WR to WR Timings (TC_WRWR_0_0_0_MCHBAR) Roundtrip Latency (SC_Roundtrip_latency_0_0_0_MCHBAR) ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR) ECC Error Log 1 (ECCERRLOG1_0_0_0_MCHBAR) Power Down Timing (TC_PWRDN_0_0_0_MCHBAR) CAS Timing (TC_CAS_0_0_0_MCHBAR) ODT Matrix (SC_ODT_MATRIX_0_0_0_MCHBAR) Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR) WCK Timing (TC_WCK_0_0_0_MCHBAR) ACT Command Timing (TC_ACT_0_0_0_MCHBAR)
PRE Command Timing (TC_PRE_0_0_0_MCHBAR)
RD to RD Timings (TC_RDRD_0_0_0_MCHBAR)
RD to WR Timings (TC_RDWR_0_0_0_MCHBAR)
WR to RD Timings (TC_WRRD_0_0_0_MCHBAR)
WR to WR Timings (TC_WRWR_0_0_0_MCHBAR)
Roundtrip Latency (SC_Roundtrip_latency_0_0_0_MCHBAR)
ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR)
ECC Error Log 1 (ECCERRLOG1_0_0_0_MCHBAR)
Power Down Timing (TC_PWRDN_0_0_0_MCHBAR)
CAS Timing (TC_CAS_0_0_0_MCHBAR)
ODT Matrix (SC_ODT_MATRIX_0_0_0_MCHBAR)
Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR)
WCK Timing (TC_WCK_0_0_0_MCHBAR)
ACT Command Timing (TC_ACT_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4) TC REFm 0 0 0 MCHBAR (TC_REFm_0_0_0_MCHBAR) Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR) Refresh Parameters (RFP_0_0_0_MCHBAR) ZQCAL Control (TC_ZQCAL_0_0_0_MCHBAR) Miscellaneous MR (TC_MR_0_0_0_MCHBAR) Refresh Timing Parameters (TC_RFTP_0_0_0_MCHBAR) Self-Refresh Exit Timing Parameters (TC_SREXITTP_0_0_0_MCHBAR) Read/Write Retraining (TC_RETRAINING_OSCL_0_0_0_MCHBAR) ECC Inject Count (ECC_Inject_count_0_0_0_MCHBAR)
TC REFm 0 0 0 MCHBAR (TC_REFm_0_0_0_MCHBAR)
Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
Refresh Parameters (RFP_0_0_0_MCHBAR)
ZQCAL Control (TC_ZQCAL_0_0_0_MCHBAR)
Miscellaneous MR (TC_MR_0_0_0_MCHBAR)
Refresh Timing Parameters (TC_RFTP_0_0_0_MCHBAR)
Self-Refresh Exit Timing Parameters (TC_SREXITTP_0_0_0_MCHBAR)
Read/Write Retraining (TC_RETRAINING_OSCL_0_0_0_MCHBAR)
ECC Inject Count (ECC_Inject_count_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5) MemSS PMA BIOS memory configuration register (MEMSS_PMA_CR_BIOS_MEM_CONFIG) MemSS PMA memory configuration register (MEMSS_PMA_CR_MEM_CONFIG) MemSS PMA BIOS request register (MEMSS_PMA_CR_BIOS_REQ) MemSS PMA init state register (MEMSS_PMA_CR_INIT_STATE) MemSS PMA BIOS data register (MEMSS_PMA_CR_BIOS_DATA) MemSS PMA BIOS mailbox register (MEMSS_PMA_CR_BIOS_MAILBOX) MemSS PMA BIOS error status register (MEMSS_PMA_CR_BIOS_ERROR_STATUS) BIOS MRC Revision (MEMSS_PMA_CR_MRC_VERSION) Countdown Timer (MEMSS_PMA_CR_COUNTDOWN_TIMER) Counter increments by 1 every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Lo) Counter increments by overflow value of PKG_MC_C0_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Hi) Counter increments by CMI PLL ratio every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Lo) Counter increments by overflow value of PKG_MC_C0_RATIO_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Hi)
MemSS PMA BIOS memory configuration register (MEMSS_PMA_CR_BIOS_MEM_CONFIG)
MemSS PMA memory configuration register (MEMSS_PMA_CR_MEM_CONFIG)
MemSS PMA BIOS request register (MEMSS_PMA_CR_BIOS_REQ)
MemSS PMA init state register (MEMSS_PMA_CR_INIT_STATE)
MemSS PMA BIOS data register (MEMSS_PMA_CR_BIOS_DATA)
MemSS PMA BIOS mailbox register (MEMSS_PMA_CR_BIOS_MAILBOX)
MemSS PMA BIOS error status register (MEMSS_PMA_CR_BIOS_ERROR_STATUS)
BIOS MRC Revision (MEMSS_PMA_CR_MRC_VERSION)
Countdown Timer (MEMSS_PMA_CR_COUNTDOWN_TIMER)
Counter increments by 1 every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Lo)
Counter increments by overflow value of PKG_MC_C0_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Hi)
Counter increments by CMI PLL ratio every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Lo)
Counter increments by overflow value of PKG_MC_C0_RATIO_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Hi)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1) BIOS POST Code (BIOS_POST_CODE_0_0_0_MCHBAR_PCU) (DDR_PTM_CTL_0_0_0_MCHBAR_PCU) Package RAPL Performance Status (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU) GT IA Performance BIAS (GT_IA_PERF_BIAS_0_0_0_MCHBAR_PCU) Secondary Plane Turbo Policy (SECP_TURBO_PLCY_0_0_0_MCHBAR_PCU) Primary Plane Energy Status (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU) Secondary Plane Energy Status (SECP_NRG_STTS_0_0_0_MCHBAR_PCU) Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU) Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU) Primary Plane 0 Temperature (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU) RP-State Limits (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU) Package Power Limit (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU) Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) BIOS Mailbox Data (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU) BIOS Mailbox Interface (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU) BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) Configurable TDP Nominal (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU) Configurable TDP Level 1 (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU) Configurable TDP Level 2 (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU) Configurable TDP Control (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU) Turbo Activation Ratio (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU) Overclocking Status (OC_STATUS_0_0_0_MCHBAR_PCU) Base Clock (BCLK) Frequency (BCLK_FREQ_0_0_0_MCHBAR)
BIOS POST Code (BIOS_POST_CODE_0_0_0_MCHBAR_PCU)
(DDR_PTM_CTL_0_0_0_MCHBAR_PCU)
Package RAPL Performance Status (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU)
GT IA Performance BIAS (GT_IA_PERF_BIAS_0_0_0_MCHBAR_PCU)
Secondary Plane Turbo Policy (SECP_TURBO_PLCY_0_0_0_MCHBAR_PCU)
Primary Plane Energy Status (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU)
Secondary Plane Energy Status (SECP_NRG_STTS_0_0_0_MCHBAR_PCU)
Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU)
Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU)
Primary Plane 0 Temperature (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU)
RP-State Limits (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU)
Package Power Limit (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU)
Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU)
BIOS Mailbox Data (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU)
BIOS Mailbox Interface (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU)
BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU)
Configurable TDP Nominal (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU)
Configurable TDP Level 1 (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU)
Configurable TDP Level 2 (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU)
Configurable TDP Control (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU)
Turbo Activation Ratio (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU)
Overclocking Status (OC_STATUS_0_0_0_MCHBAR_PCU)
Base Clock (BCLK) Frequency (BCLK_FREQ_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2) Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU) Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU) Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_0_0_MCHBAR_PCU) Cycle Sum of Overlapping Active GT and Core (DMU_IA_GT_OVERLAP_0_0_0_MCHBAR_PCU) Cycle Sum of Overlapping Active Media and Core (DMU_IA_MEDIA_OVERLAP_0_0_0_MCHBAR_PCU) Cycle Sum of Any Active Core (CDIE_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU) System Agent Performance Status (SA_PERF_STATUS_0_0_0_MCHBAR_PCU) GT Performance Status (GT_PERF_STATUS_0_0_0_MCHBAR_PCU) Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU) RP-State Capability (RP_STATE_CAP_0_0_0_MCHBAR_PCU) Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU) Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU) Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU) (CORE_PERF_MIN_MAX_0_0_0_MCHBAR)
Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU)
Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active GT and Core (DMU_IA_GT_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active Media and Core (DMU_IA_MEDIA_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Any Active Core (CDIE_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU)
System Agent Performance Status (SA_PERF_STATUS_0_0_0_MCHBAR_PCU)
GT Performance Status (GT_PERF_STATUS_0_0_0_MCHBAR_PCU)
Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU)
RP-State Capability (RP_STATE_CAP_0_0_0_MCHBAR_PCU)
Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU)
Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU)
Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU)
(CORE_PERF_MIN_MAX_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) General Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR) Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR) Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR) Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR) Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR) Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR) Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR) Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR) Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR) Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR) Enhanced Command (ECMD_0_0_0_VTDBAR) Enhanced Command Response (ERESP_0_0_0_VTDBAR) Enhanced Command Status (ESTS0_0_0_0_VTDBAR) Enhanced Command Status (ESTS1_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP0_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP1_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP2_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR) Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR) Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR) Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
Version Register (VER_REG_0_0_0_VTDBAR)
Capability Register (CAP_REG_0_0_0_VTDBAR)
Extended Capability Register (ECAP_REG_0_0_0_VTDBAR)
Global Command Register (GCMD_REG_0_0_0_VTDBAR)
General Status Register (GSTS_REG_0_0_0_VTDBAR)
Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR)
Context Command Register (CCMD_REG_0_0_0_VTDBAR)
Fault Status Register (FSTS_REG_0_0_0_VTDBAR)
Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR)
Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR)
Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR)
Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR)
Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR)
Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR)
Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR)
Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR)
Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR)
Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR)
Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR)
Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR)
Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR)
Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR)
Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR)
Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR)
Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR)
Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR)
IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR)
Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR)
Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR)
Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR)
Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR)
Page Request Status Register (PRS_REG_0_0_0_VTDBAR)
Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR)
Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR)
Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR)
Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR)
MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR)
MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR)
Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR)
Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR)
Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR)
Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR)
Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR)
Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR)
Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR)
Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR)
Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR)
Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR)
Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR)
Enhanced Command (ECMD_0_0_0_VTDBAR)
Enhanced Command Response (ERESP_0_0_0_VTDBAR)
Enhanced Command Status (ESTS0_0_0_0_VTDBAR)
Enhanced Command Status (ESTS1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP0_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP2_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR)
Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR)
Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR)
Invalidate Address Register (IVA_REG_0_0_0_VTDBAR)
IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR)
Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR)
Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR)
Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
D10:F0 Platform Monitoring Technology (PMT) Registers
D10:F0 Platform Monitoring Technology (PMT) Registers Device ID and Vendor ID (VENDOR_ID_DEVICE_ID) Command and Status (COMMAND_STATUS) Revision ID and Class Code (REVISION_ID) Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE) Base Address (PM_BAR) Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID) Capabilities Pointer (CAPABILITIES_POINTER) Interrupt line (INTERRUPT_LINE) PCIe Capability ID (PCIE_CAPID) Device Capabilities (DEV_CAP) PCIE Device Control and Status (DEV_CTL_STS) Power Management Capabilities (PM_CAPID) Power Management Control Status (PM_CONTROL_STATUS) Telemetry Capability Header (TELEM_CAPABILITY_HEADER) Telemetry VSEC 0 (TELEM_VSEC_0) Telemetry VSEC 1 (TELEM_VSEC_1) Telemetry VSEC 2 (TELEM_VSEC_2) Watcher Capability Header (WATCHER_CAPABILITY_HEADER) Watcher VSEC 0 (WATCHER_VSEC_0) Watcher VSEC 1 (WATCHER_VSEC_1) Watcher VSEC 2 (WATCHER_VSEC_2) Crashlog Capability Header (CRASHLOG_CAPABILITY_HEADER) Crashlog VSEC 0 (CRASHLOG_VSEC_0) Crashlog VSEC 1 (CRASHLOG_VSEC_1) Crashlog VSEC 2 (CRASHLOG_VSEC_2)
Device ID and Vendor ID (VENDOR_ID_DEVICE_ID)
Command and Status (COMMAND_STATUS)
Revision ID and Class Code (REVISION_ID)
Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE)
Base Address (PM_BAR)
Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID)
Capabilities Pointer (CAPABILITIES_POINTER)
Interrupt line (INTERRUPT_LINE)
PCIe Capability ID (PCIE_CAPID)
Device Capabilities (DEV_CAP)
PCIE Device Control and Status (DEV_CTL_STS)
Power Management Capabilities (PM_CAPID)
Power Management Control Status (PM_CONTROL_STATUS)
Telemetry Capability Header (TELEM_CAPABILITY_HEADER)
Telemetry VSEC 0 (TELEM_VSEC_0)
Telemetry VSEC 1 (TELEM_VSEC_1)
Telemetry VSEC 2 (TELEM_VSEC_2)
Watcher Capability Header (WATCHER_CAPABILITY_HEADER)
Watcher VSEC 0 (WATCHER_VSEC_0)
Watcher VSEC 1 (WATCHER_VSEC_1)
Watcher VSEC 2 (WATCHER_VSEC_2)
Crashlog Capability Header (CRASHLOG_CAPABILITY_HEADER)
Crashlog VSEC 0 (CRASHLOG_VSEC_0)
Crashlog VSEC 1 (CRASHLOG_VSEC_1)
Crashlog VSEC 2 (CRASHLOG_VSEC_2)
D11:F0 Vision Processing Unit
D11:F0 Vision Processing Unit Device ID and Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision ID and Class Code (REVCLASSCODE) Cache Line Latency Header and BIST (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Base Address Register (BAR2) Base Address Register High (BAR2_HIGH) Subsystem Vendor and Subsystem ID (SUBSYSTEMID) Expansion ROM Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt (INTERRUPTREG) PCIe Capabilities (PCIECAPREG) PCIe Device Capability (DEVCAPREG) PCIe Device Control Status (DEVCTRLSTAT) PCIe Device Capability2 (DEVCAPREG2) PCIe Device Control2 Status (DEVCTRLSTAT2) Power Management Capability ID (POWERCAPID) Power Management Control And Status (PMECTRLSTATUS) PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write 1 (GEN_PCI_REGRW1) General Purpose Read Write 2 (GEN_PCI_REGRW2) General Purpose Read Write 3 (GEN_PCI_REGRW3) General Purpose Read Write 4 (GEN_PCI_REGRW4) General Purpose Input (GEN_INPUT_REG) Msix Capability (MSIX_CAP_REG) MSIX Table Pointer (MSIX_TABLE_PTR) MSIX PBA Pointer (MSIX_PBA_PTR) MSI Capability (MSI_CAP_REG) MSI Message Low Address (MSI_ADDR_LOW) MSI Message High Address (MSI_ADDR_HIGH) MSI Message Data (MSI_MSG_DATA) MSI Mask (MSI_MASK) MSI Pending (MSI_PENDING) VTDBAR Base Low Address (VTDBAR_LOW) VTdBAR Base High Address (VTDBAR_HIGH) Manufacturers ID (MANID) ATS Extended Capability Header (ATS_EXT_CAP_HEAD) ATS Capability and Control (ATS_CAP_CONTROL_HEAD) SRIOV PCIE Capability (SRIOV_PCIE_CAP_ID) SRIOV Capability (SRIOV_CAP) SRIOV Control And Status (SRIOV_CTRL_STATUS) Initial and Total VF (TOT_INIT_VF) NUMVF And Function Dependency Link (NUMVF_SRIOV_FUN_DEP_LINK) VF Offset Stride (VF_OFFSET_STRIDE) VF Device ID (VF_DEVICE_ID) SRIOV Supported Page Size (SRIOV_SUP_PAGE_SIZE) SRIOV System Page Size (SRIOV_SYSTEM_PAGE_SIZE) VF Base Address Low (VF_BASE_ADDR_REG_LOW) VF Base Address High (VF_BASE_ADDR_REG_HI) VF Migration Array (VF_MIGRATION_ARRAY)
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Base Address Register (BAR2)
Base Address Register High (BAR2_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
PCIe Capabilities (PCIECAPREG)
PCIe Device Capability (DEVCAPREG)
PCIe Device Control Status (DEVCTRLSTAT)
PCIe Device Capability2 (DEVCAPREG2)
PCIe Device Control2 Status (DEVCTRLSTAT2)
Power Management Capability ID (POWERCAPID)
Power Management Control And Status (PMECTRLSTATUS)
PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG)
Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_PCI_REGRW1)
General Purpose Read Write 2 (GEN_PCI_REGRW2)
General Purpose Read Write 3 (GEN_PCI_REGRW3)
General Purpose Read Write 4 (GEN_PCI_REGRW4)
General Purpose Input (GEN_INPUT_REG)
Msix Capability (MSIX_CAP_REG)
MSIX Table Pointer (MSIX_TABLE_PTR)
MSIX PBA Pointer (MSIX_PBA_PTR)
MSI Capability (MSI_CAP_REG)
MSI Message Low Address (MSI_ADDR_LOW)
MSI Message High Address (MSI_ADDR_HIGH)
MSI Message Data (MSI_MSG_DATA)
MSI Mask (MSI_MASK)
MSI Pending (MSI_PENDING)
VTDBAR Base Low Address (VTDBAR_LOW)
VTdBAR Base High Address (VTDBAR_HIGH)
Manufacturers ID (MANID)
ATS Extended Capability Header (ATS_EXT_CAP_HEAD)
ATS Capability and Control (ATS_CAP_CONTROL_HEAD)
SRIOV PCIE Capability (SRIOV_PCIE_CAP_ID)
SRIOV Capability (SRIOV_CAP)
SRIOV Control And Status (SRIOV_CTRL_STATUS)
Initial and Total VF (TOT_INIT_VF)
NUMVF And Function Dependency Link (NUMVF_SRIOV_FUN_DEP_LINK)
VF Offset Stride (VF_OFFSET_STRIDE)
VF Device ID (VF_DEVICE_ID)
SRIOV Supported Page Size (SRIOV_SUP_PAGE_SIZE)
SRIOV System Page Size (SRIOV_SYSTEM_PAGE_SIZE)
VF Base Address Low (VF_BASE_ADDR_REG_LOW)
VF Base Address High (VF_BASE_ADDR_REG_HI)
VF Migration Array (VF_MIGRATION_ARRAY)
D14:F0 Volume Management Device
D14:F0 Volume Management Device Vendor ID (VID_0_14_0_PCI) Device ID (DID_0_14_0_PCI) PCI Command (PCICMD_0_14_0_PCI) PCI Status (PCISTS_0_14_0_PCI) Revision ID (RID_0_14_0_PCI) Class Code (CCRIF_0_14_0_PCI) Class Code Register Classes (CCRC_0_14_0_PCI) Cache Line Size (CLSR_0_14_0_PCI) Header Type (HDR_0_14_0_PCI) VMD Configuration Base Address (CFGBAR_0_14_0_PCI) VMD Memory Base Address Range 1 (MEMBAR1_0_14_0_PCI) VMD Memory Base Address Range 2 (MEMBAR2_0_14_0_PCI) Subsystem Vendor ID (SVID_0_14_0_PCI) Subsystem ID (SSID_0_14_0_PCI) Capabilities Pointer (CAPPTR_0_14_0_PCI) Interrupt Line Register (INTL_0_14_0_PCI) Interrupt Pin Register (INTPIN_0_14_0_PCI) VMCAP (VMCAP_0_14_0_PCI) VMCONFIG (VMCONFIG_0_14_0_PCI) VMASSIGN (VMASSIGN_0_14_0_PCI) CFGBARSZ (CFGBARSZ_0_14_0_PCI) MEMBAR1SZ (MEMBAR1SZ_0_14_0_PCI) MEMBARxSZ (MEMBAR2SZ_0_14_0_PCI) ROOTBUS (ROOTBUS_0_14_0_PCI) FNx_ASSIGN (FN0_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN1_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN2_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN3_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN4_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN5_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN6_ASSIGN_0_14_0_PCI) FNx_ASSIGN (FN7_ASSIGN_0_14_0_PCI) VMASSIGN (VMASSIGN_ROOTBUS1_0_14_0_PCI) ROOTBUS1 (ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN0_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN1_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN2_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN3_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN4_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN5_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN6_ASSIGN_ROOTBUS1_0_14_0_PCI) FNx_ASSIGN (FN7_ASSIGN_ROOTBUS1_0_14_0_PCI) BUS RANGE ROOTBUS0 register (BUS_RANGE_ROOTBUS0_0_14_0_PCI) BUS RANGE ROOTBUS1 register (BUS_RANGE_ROOTBUS1_0_14_0_PCI) MEMBAR1 Offset for Rootbus1 (MEMBAR1_OFFSET_ROOTBUS1_0_14_0_PCI) MEMBAR2 Offset for Rootbus1 (MEMBAR2_OFFSET_ROOTBUS1_0_14_0_PCI)
Vendor ID (VID_0_14_0_PCI)
Device ID (DID_0_14_0_PCI)
PCI Command (PCICMD_0_14_0_PCI)
PCI Status (PCISTS_0_14_0_PCI)
Revision ID (RID_0_14_0_PCI)
Class Code (CCRIF_0_14_0_PCI)
Class Code Register Classes (CCRC_0_14_0_PCI)
Cache Line Size (CLSR_0_14_0_PCI)
Header Type (HDR_0_14_0_PCI)
VMD Configuration Base Address (CFGBAR_0_14_0_PCI)
VMD Memory Base Address Range 1 (MEMBAR1_0_14_0_PCI)
VMD Memory Base Address Range 2 (MEMBAR2_0_14_0_PCI)
Subsystem Vendor ID (SVID_0_14_0_PCI)
Subsystem ID (SSID_0_14_0_PCI)
Capabilities Pointer (CAPPTR_0_14_0_PCI)
Interrupt Line Register (INTL_0_14_0_PCI)
Interrupt Pin Register (INTPIN_0_14_0_PCI)
VMCAP (VMCAP_0_14_0_PCI)
VMCONFIG (VMCONFIG_0_14_0_PCI)
VMASSIGN (VMASSIGN_0_14_0_PCI)
CFGBARSZ (CFGBARSZ_0_14_0_PCI)
MEMBAR1SZ (MEMBAR1SZ_0_14_0_PCI)
MEMBARxSZ (MEMBAR2SZ_0_14_0_PCI)
ROOTBUS (ROOTBUS_0_14_0_PCI)
FNx_ASSIGN (FN0_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN1_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN2_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN3_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN4_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN5_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN6_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN7_ASSIGN_0_14_0_PCI)
VMASSIGN (VMASSIGN_ROOTBUS1_0_14_0_PCI)
ROOTBUS1 (ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN0_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN1_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN2_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN3_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN4_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN5_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN6_ASSIGN_ROOTBUS1_0_14_0_PCI)
FNx_ASSIGN (FN7_ASSIGN_ROOTBUS1_0_14_0_PCI)
BUS RANGE ROOTBUS0 register (BUS_RANGE_ROOTBUS0_0_14_0_PCI)
BUS RANGE ROOTBUS1 register (BUS_RANGE_ROOTBUS1_0_14_0_PCI)
MEMBAR1 Offset for Rootbus1 (MEMBAR1_OFFSET_ROOTBUS1_0_14_0_PCI)
MEMBAR2 Offset for Rootbus1 (MEMBAR2_OFFSET_ROOTBUS1_0_14_0_PCI)
D14:F0 Volume Management Device MEMBAR2
D14:F0 Volume Management Device MEMBAR2 MSI-X Table Address Register 0 (MSIXADDR_0_14_0_MEMBAR2[0]) MSI-X Message Data Register 0 (MSIXDATA_0_14_0_MEMBAR2[0]) MSI-X Vector Control Register 0 (MSIXVCTL_0_14_0_MEMBAR2[0]) MSI-X Pending Bit Array (MSIXPBA_0_14_0_MEMBAR2)
MSI-X Table Address Register 0 (MSIXADDR_0_14_0_MEMBAR2[0])
MSI-X Message Data Register 0 (MSIXDATA_0_14_0_MEMBAR2[0])
MSI-X Vector Control Register 0 (MSIXVCTL_0_14_0_MEMBAR2[0])
MSI-X Pending Bit Array (MSIXPBA_0_14_0_MEMBAR2)
D2:F0 Processor Graphics
D2:F0 Processor Graphics Vendor Identification (VID2_0_2_0_PCI) Device Identification (DID2_0_2_0_PCI) PCI Command (PCICMD_0_2_0_PCI) PCI Status (PCISTS2_0_2_0_PCI) Revision Identification and Class Code register (RID2_CC_0_2_0_PCI) Cache Line Size (CLS_0_2_0_PCI) Master Latency Timer (MLT2_0_2_0_PCI) Header Type (HDR2_0_2_0_PCI) Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI) Local Memory Bar (LMEMBAR0_0_2_0_PCI) Local Memory Bar (LMEMBAR1_0_2_0_PCI) Subsystem Vendor Identification (SVID2_0_2_0_PCI) Subsystem Identification (SID2_0_2_0_PCI) Capabilities Pointer (CAPPOINT_0_2_0_PCI) Interrupt Line (INTRLINE_0_2_0_PCI) Interrupt Pin (INTRPIN_0_2_0_PCI) Minimum Grant (MINGNT_0_2_0_PCI) Maximum Latency (MAXLAT_0_2_0_PCI) Capability Identifier (CAPID0_0_2_0_PCI) Capabilities Control (CAPCTRL0_0_2_0_PCI) Capabilities A (CAPID0_A_0_2_0_PCI) Capabilities B (CAPID0_B_0_2_0_PCI) PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI) Device 2 Control (DEV2CTL_0_2_0_PCI) VTd Status (VTD_STATUS_0_2_0_PCI) PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI) PCI Express Capability (PCIECAP_0_2_0_PCI) Device Capabilities (DEVICECAP_0_2_0_PCI) PCI Express Device Control (DEVICECTL_0_2_0_PCI) PCI Express Device Status Register (DEVICESTS_0_2_0_PCI) Link Capabilities (LINKCAP_0_2_0_PCI) Link Control and Status (LINKCTRLSTS_0_2_0_PCI) Device Capabilities 2 (DEVCAP2_0_2_0_PCI) Device Control 2 (DEVCTRL2_0_2_0_PCI) Link Capabilities 2 (LINKCAP2_0_2_0_PCI) Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI) Message Control (MC_0_2_0_PCI) Message Address (MA0_0_2_0_PCI) Message Address (MA1_0_2_0_PCI) Message Data (MD_0_2_0_PCI) MSI Mask Bits (MSI_MASK_0_2_0_PCI) MSI Pending Bits (MSI_PEND_0_2_0_PCI) Power Management Capabilities ID (PMCAPID_0_2_0_PCI) Power Management Capabilities (PMCAP_0_2_0_PCI) Power Management Control and Status (PMCS_0_2_0_PCI) Graphics System Event (GSE_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI) Stepping Revision ID (SRID_0_2_0_PCI) ASL Storage (ASLS_0_2_0_PCI) ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI) ARI Capability (ARI_CAP_0_2_0_PCI) ARI Control (ARI_CTRL_0_2_0_PCI) PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI) PASID Capability (PASID_CAP_0_2_0_PCI) PASID Control (PASID_CTRL_0_2_0_PCI) ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI) ATS Capability (ATS_CAP_0_2_0_PCI) ATS Control (ATS_CTRL_0_2_0_PCI) Page Request Extended Capability Header (PR_EXTCAP_0_2_0_PCI) Page Request Control (PR_CTRL_0_2_0_PCI) Page Request Status (PR_STATUS_0_2_0_PCI) Outstanding Page Request Capacity (OPRC_0_2_0_PCI) Outstanding Page Request Allocation (OPRA_0_2_0_PCI) SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI) SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI) SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI) SRIOV Status (SRIOV_STS_0_2_0_PCI) SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI) SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI) Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI) First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI) VF Stride (VF_STRIDE_0_2_0_PCI) VF Device ID (VF_DEVICEID_0_2_0_PCI) Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI) System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI) VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI) VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI) VF Migration State Array Offset (VF_MIGST_OFFSET_0_2_0_PCI) LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI) Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI) Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI) PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI) PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI) PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)
Vendor Identification (VID2_0_2_0_PCI)
Device Identification (DID2_0_2_0_PCI)
PCI Command (PCICMD_0_2_0_PCI)
PCI Status (PCISTS2_0_2_0_PCI)
Revision Identification and Class Code register (RID2_CC_0_2_0_PCI)
Cache Line Size (CLS_0_2_0_PCI)
Master Latency Timer (MLT2_0_2_0_PCI)
Header Type (HDR2_0_2_0_PCI)
Built In Self Test (BIST_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI)
Local Memory Bar (LMEMBAR0_0_2_0_PCI)
Local Memory Bar (LMEMBAR1_0_2_0_PCI)
Subsystem Vendor Identification (SVID2_0_2_0_PCI)
Subsystem Identification (SID2_0_2_0_PCI)
Capabilities Pointer (CAPPOINT_0_2_0_PCI)
Interrupt Line (INTRLINE_0_2_0_PCI)
Interrupt Pin (INTRPIN_0_2_0_PCI)
Minimum Grant (MINGNT_0_2_0_PCI)
Maximum Latency (MAXLAT_0_2_0_PCI)
Capability Identifier (CAPID0_0_2_0_PCI)
Capabilities Control (CAPCTRL0_0_2_0_PCI)
Capabilities A (CAPID0_A_0_2_0_PCI)
Capabilities B (CAPID0_B_0_2_0_PCI)
PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI)
Device 2 Control (DEV2CTL_0_2_0_PCI)
VTd Status (VTD_STATUS_0_2_0_PCI)
PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI)
PCI Express Capability (PCIECAP_0_2_0_PCI)
Device Capabilities (DEVICECAP_0_2_0_PCI)
PCI Express Device Control (DEVICECTL_0_2_0_PCI)
PCI Express Device Status Register (DEVICESTS_0_2_0_PCI)
Link Capabilities (LINKCAP_0_2_0_PCI)
Link Control and Status (LINKCTRLSTS_0_2_0_PCI)
Device Capabilities 2 (DEVCAP2_0_2_0_PCI)
Device Control 2 (DEVCTRL2_0_2_0_PCI)
Link Capabilities 2 (LINKCAP2_0_2_0_PCI)
Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI)
Message Control (MC_0_2_0_PCI)
Message Address (MA0_0_2_0_PCI)
Message Address (MA1_0_2_0_PCI)
Message Data (MD_0_2_0_PCI)
MSI Mask Bits (MSI_MASK_0_2_0_PCI)
MSI Pending Bits (MSI_PEND_0_2_0_PCI)
Power Management Capabilities ID (PMCAPID_0_2_0_PCI)
Power Management Capabilities (PMCAP_0_2_0_PCI)
Power Management Control and Status (PMCS_0_2_0_PCI)
Graphics System Event (GSE_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI)
Stepping Revision ID (SRID_0_2_0_PCI)
ASL Storage (ASLS_0_2_0_PCI)
ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI)
ARI Capability (ARI_CAP_0_2_0_PCI)
ARI Control (ARI_CTRL_0_2_0_PCI)
PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI)
PASID Capability (PASID_CAP_0_2_0_PCI)
PASID Control (PASID_CTRL_0_2_0_PCI)
ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI)
ATS Capability (ATS_CAP_0_2_0_PCI)
ATS Control (ATS_CTRL_0_2_0_PCI)
Page Request Extended Capability Header (PR_EXTCAP_0_2_0_PCI)
Page Request Control (PR_CTRL_0_2_0_PCI)
Page Request Status (PR_STATUS_0_2_0_PCI)
Outstanding Page Request Capacity (OPRC_0_2_0_PCI)
Outstanding Page Request Allocation (OPRA_0_2_0_PCI)
SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI)
SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI)
SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI)
SRIOV Status (SRIOV_STS_0_2_0_PCI)
SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI)
SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI)
Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI)
First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI)
VF Stride (VF_STRIDE_0_2_0_PCI)
VF Device ID (VF_DEVICEID_0_2_0_PCI)
Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI)
System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI)
VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI)
VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI)
VF Migration State Array Offset (VF_MIGST_OFFSET_0_2_0_PCI)
LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI)
Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI)
Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI)
PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI)
PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI)
PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)
D4:F0 Dynamic Tuning Technology
D4:F0 Dynamic Tuning Technology Vendor ID (VID_0_4_0_PCI) Device ID (DID_0_4_0_PCI) PCI Command (PCICMD_0_4_0_PCI) PCI Status (PCISTS_0_4_0_PCI) Revision ID (RID_0_4_0_PCI) Class Code (CC_0_4_0_PCI) Extended Class Code (CC_0_4_0_NOPI_PCI) Cache Line Size (CLS_0_4_0_PCI) Master Latency Timer (MLT_0_4_0_PCI) Header Type (HDR_0_4_0_PCI) Built In Self Test (BIST_0_4_0_PCI) Thermal Controller Base Address (TMBAR_0_4_0_PCI) Subsystem Vendor ID (SVID_0_4_0_PCI) Subsystem ID (SID_0_4_0_PCI) Capabilities Pointer (CAPPOINT_0_4_0_PCI) Interrupt Line Register (INTRLINE_0_4_0_PCI) Interrupt Pin Register (INTRPIN_0_4_0_PCI) Minimum Guaranteed (MINGNT_0_4_0_PCI) Maximum Latency (MAXLAT_0_4_0_PCI) Device Enable (DEVEN_0_4_0_PCI) Capabilities A (CAPID0_A_0_4_0_PCI) Capabilities B (CAPID0_B_0_4_0_PCI)
Vendor ID (VID_0_4_0_PCI)
Device ID (DID_0_4_0_PCI)
PCI Command (PCICMD_0_4_0_PCI)
PCI Status (PCISTS_0_4_0_PCI)
Revision ID (RID_0_4_0_PCI)
Class Code (CC_0_4_0_PCI)
Extended Class Code (CC_0_4_0_NOPI_PCI)
Cache Line Size (CLS_0_4_0_PCI)
Master Latency Timer (MLT_0_4_0_PCI)
Header Type (HDR_0_4_0_PCI)
Built In Self Test (BIST_0_4_0_PCI)
Thermal Controller Base Address (TMBAR_0_4_0_PCI)
Subsystem Vendor ID (SVID_0_4_0_PCI)
Subsystem ID (SID_0_4_0_PCI)
Capabilities Pointer (CAPPOINT_0_4_0_PCI)
Interrupt Line Register (INTRLINE_0_4_0_PCI)
Interrupt Pin Register (INTRPIN_0_4_0_PCI)
Minimum Guaranteed (MINGNT_0_4_0_PCI)
Maximum Latency (MAXLAT_0_4_0_PCI)
Device Enable (DEVEN_0_4_0_PCI)
Capabilities A (CAPID0_A_0_4_0_PCI)
Capabilities B (CAPID0_B_0_4_0_PCI)

D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers

This chapter documents the VTDPVC0 BAR registers.
Base address of these registers are defined in the VTDPVC0BAR_​0_​0_​0_​MCHBAR_​NCU register which resides in the MCHBAR register collection.
VTDPVC0BAR is 8KB in size and is supported 2 sets of IOMMU registers:
Set1 offset range 0x0000 – 0xF88
Set2 offset range 0x1000 – 0x10F88

Summary of Bus: (), Device: (), Function: (), Type: (MEM)

Offset

Size (Bytes)

Register Name (Register Symbol)

Scope

Default Value

0h

4

Version Register (VER_​REG_​0_​0_​0_​VTDBAR)

package

00000070h

8h

8

Capability Register (CAP_​REG_​0_​0_​0_​VTDBAR)

package

E9DE008CEE690462h

10h

8

Extended Capability Register (ECAP_​REG_​0_​0_​0_​VTDBAR)

package

001ACA9A04F0EFDEh

18h

4

Global Command Register (GCMD_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

1ch

4

General Status Register (GSTS_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

20h

8

Root Table Address Register (RTADDR_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

28h

8

Context Command Register (CCMD_​REG_​0_​0_​0_​VTDBAR)

package

0800000000000000h

34h

4

Fault Status Register (FSTS_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

38h

4

Fault Event Control Register (FECTL_​REG_​0_​0_​0_​VTDBAR)

package

80000000h

3ch

4

Fault Event Data Register (FEDATA_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

40h

4

Fault Event Address Register (FEADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

44h

4

Fault Event Upper Address Register (FEUADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

58h

8

Advanced Fault Log Register (AFLOG_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

64h

4

Protected Memory Enable Register (PMEN_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

68h

4

Protected Low Memory Base Register (PLMBASE_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

6ch

4

Protected Low-Memory Limit Register (PLMLIMIT_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

70h

8

Protected High-Memory Base Register (PHMBASE_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

78h

8

Protected High-Memory Limit Register (PHMLIMIT_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

80h

8

Invalidation Queue Head Register (IQH_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

88h

8

Invalidation Queue Tail Register (IQT_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

90h

8

Invalidation Queue Address Register (IQA_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

9ch

4

Invalidation Completion Status Register (ICS_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

a0h

4

Invalidation Event Control Register (IECTL_​REG_​0_​0_​0_​VTDBAR)

package

80000000h

a4h

4

Invalidation Event Data Register (IEDATA_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

a8h

4

Invalidation Event Address Register (IEADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

ach

4

Invalidation Event Upper Address Register (IEUADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

b0h

8

IQ Error Info register (IQERCD_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

b8h

8

Interrupt Remapping Table Address Register (IRTA_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

c0h

8

Page Request Queue Head Register (PQH_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

c8h

8

Page Request Queue Tail Register (PQT_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

d0h

8

Page Request Queue Address Register (PQA_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

dch

4

Page Request Status Register (PRS_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

e0h

4

Page Request Event Control Register (PECTL_​REG_​0_​0_​0_​VTDBAR)

package

80000000h

e4h

4

Page Request Event Data Register (PEDATA_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

e8h

4

Page Request Event Address Register (PEADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

ech

4

Page Request Event Upper Address Register (PEUADDR_​REG_​0_​0_​0_​VTDBAR)

package

00000000h

100h

8

MTRR Capability Register (MTRRCAP_​0_​0_​0_​VTDBAR)

package

000000000000050Ah

108h

8

MTRR Default Type Register (MTRRDEFAULT_​0_​0_​0_​VTDBAR)

package

0000000000000000h

120h

8

Fixed-Range MTRR Format 64K-00000 (MTRR_​FIX64K_​00000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

128h

8

Fixed-Range MTRR Format 16K-80000 (MTRR_​FIX16K_​80000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

130h

8

Fixed-Range MTRR Format 16K-A0000 (MTRR_​FIX16K_​A0000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

138h

8

Fixed-Range MTRR Format 4K-C0000 (MTRR_​FIX4K_​C0000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

140h

8

Fixed-Range MTRR Format 4K-C8000 (MTRR_​FIX4K_​C8000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

148h

8

Fixed-Range MTRR Format 4K-D0000 (MTRR_​FIX4K_​D0000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

150h

8

Fixed-Range MTRR Format 4K-D8000 (MTRR_​FIX4K_​D8000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

158h

8

Fixed-Range MTRR Format 4K-E0000 (MTRR_​FIX4K_​E0000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

160h

8

Fixed-Range MTRR Format 4K-E8000 (MTRR_​FIX4K_​E8000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

168h

8

Fixed-Range MTRR Format 4K-F0000 (MTRR_​FIX4K_​F0000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

170h

8

Fixed-Range MTRR Format 4K-F8000 (MTRR_​FIX4K_​F8000_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

180h

8

Variable-Range MTRR Format Physical Base 0 (MTRR_​PHYSBASE0_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

188h

8

Variable-Range MTRR Format Physical Mask 0 (MTRR_​PHYSMASK0_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

190h

8

Variable-Range MTRR Format Physical Base 1 (MTRR_​PHYSBASE1_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

198h

8

Variable-Range MTRR Format Physical Mask 1 (MTRR_​PHYSMASK1_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1a0h

8

Variable-Range MTRR Format Physical Base 2 (MTRR_​PHYSBASE2_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1a8h

8

Variable-Range MTRR Format Physical Mask 2 (MTRR_​PHYSMASK2_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1b0h

8

Variable-Range MTRR Format Physical Base 3 (MTRR_​PHYSBASE3_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1b8h

8

Variable-Range MTRR Format Physical Mask 3 (MTRR_​PHYSMASK3_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1c0h

8

Variable-Range MTRR Format Physical Base 4 (MTRR_​PHYSBASE4_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1c8h

8

Variable-Range MTRR Format Physical Mask 4 (MTRR_​PHYSMASK4_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1d0h

8

Variable-Range MTRR Format Physical Base 5 (MTRR_​PHYSBASE5_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1d8h

8

Variable-Range MTRR Format Physical Mask 5 (MTRR_​PHYSMASK5_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1e0h

8

Variable-Range MTRR Format Physical Base 6 (MTRR_​PHYSBASE6_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1e8h

8

Variable-Range MTRR Format Physical Mask 6 (MTRR_​PHYSMASK6_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1f0h

8

Variable-Range MTRR Format Physical Base 7 (MTRR_​PHYSBASE7_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

1f8h

8

Variable-Range MTRR Format Physical Mask 7 (MTRR_​PHYSMASK7_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

200h

8

Variable-Range MTRR Format Physical Base 8 (MTRR_​PHYSBASE8_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

208h

8

Variable-Range MTRR Format Physical Mask 8 (MTRR_​PHYSMASK8_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

210h

8

Variable-Range MTRR Format Physical Base 9 (MTRR_​PHYSBASE9_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

218h

8

Variable-Range MTRR Format Physical Mask 9 (MTRR_​PHYSMASK9_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

300h

8

Performance Monitoring Capabilities (PERFCAP_​0_​0_​0_​VTDBAR)

Package

002E00180F400008h

310h

4

Performance Monitoring Configuration Offset (PERFCFGOFF_​0_​0_​0_​VTDBAR)

Package

00001000h

314h

4

Performance Monitoring Freeze Offset (PERFFRZOFF_​0_​0_​0_​VTDBAR)

Package

00001E00h

318h

4

Performance Monitoring Overflow Offset (PERFOVFOFF_​0_​0_​0_​VTDBAR)

Package

00001F00h

31ch

4

Performance Monitoring Counter Offset (PERFCNTOFF_​0_​0_​0_​VTDBAR)

Package

00002000h

324h

4

Performance Interrupt Status (PERFINTRSTS_​0_​0_​0_​VTDBAR)

Package

00000000h

328h

4

Performance Interrupt Control (PERFINTRCTL_​0_​0_​0_​VTDBAR)

Package

80000000h

32ch

4

Performance Interrupt Data (PERFINTRDATA_​0_​0_​0_​VTDBAR)

Package

00000000h

330h

4

Performance Interrupt Address (PERFINTRADDR_​0_​0_​0_​VTDBAR)

Package

00000000h

334h

4

Performance Interrupt Upper Address (PERFINTRUADDR_​0_​0_​0_​VTDBAR)

Package

00000000h

380h

8

Performance Monitoring Event Capabilities (PERFEVNTCAP0_​0_​0_​0_​VTDBAR)

Package

000000000000000Bh

388h

8

Performance Monitoring Event Capabilities (PERFEVNTCAP1_​0_​0_​0_​VTDBAR)

Package

0000000000000021h

390h

8

Performance Monitoring Event Capabilities (PERFEVNTCAP2_​0_​0_​0_​VTDBAR)

Package

00000000000000FFh

398h

8

Performance Monitoring Event Capabilities (PERFEVNTCAP3_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

3a0h

8

Performance Monitoring Event Capabilities (PERFEVNTCAP4_​0_​0_​0_​VTDBAR)

Package

0000000000000007h

400h

8

Enhanced Command (ECMD_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

410h

8

Enhanced Command Response (ERESP_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

420h

8

Enhanced Command Status (ESTS0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

428h

8

Enhanced Command Status (ESTS1_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

430h

8

Enhanced Command Capabilities (ECMD_​CAP0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

438h

8

Enhanced Command Capabilities (ECMD_​CAP1_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

440h

8

Enhanced Command Capabilities (ECMD_​CAP2_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

448h

8

Enhanced Command Capabilities (ECMD_​CAP3_​0_​0_​0_​VTDBAR)

Package

003F000000000000h

ee0h

8

Fault Recording Register Low [0] (FRCDL_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

ee8h

8

Fault Recording Register High [0] (FRCDH_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

ef0h

8

Invalidate Address Register (IVA_​REG_​0_​0_​0_​VTDBAR)

package

0000000000000000h

ef8h

8

IOTLB Invalidate Register (IOTLB_​REG_​0_​0_​0_​VTDBAR)

package

0200000000000000h

1000h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1008h

4

Performance Monitoring Filter Configuration (PERFCNTR0_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

100ch

4

Performance Monitoring Filter Configuration (PERFCNTR0_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1010h

4

Performance Monitoring Filter Configuration (PERFCNTR0_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1014h

4

Performance Monitoring Filter Configuration (PERFCNTR0_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1018h

4

Performance Monitoring Filter Configuration (PERFCNTR0_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1080h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP0_​0_​0_​0_​VTDBAR)

Package

00000000h

1100h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG1_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1108h

4

Performance Monitoring Filter Configuration (PERFCNTR1_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

110ch

4

Performance Monitoring Filter Configuration (PERFCNTR1_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1110h

4

Performance Monitoring Filter Configuration (PERFCNTR1_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1114h

4

Performance Monitoring Filter Configuration (PERFCNTR1_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1118h

4

Performance Monitoring Filter Configuration (PERFCNTR1_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1180h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP1_​0_​0_​0_​VTDBAR)

Package

00000000h

1200h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG2_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1208h

4

Performance Monitoring Filter Configuration (PERFCNTR2_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

120ch

4

Performance Monitoring Filter Configuration (PERFCNTR2_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1210h

4

Performance Monitoring Filter Configuration (PERFCNTR2_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1214h

4

Performance Monitoring Filter Configuration (PERFCNTR2_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1218h

4

Performance Monitoring Filter Configuration (PERFCNTR2_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1280h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP2_​0_​0_​0_​VTDBAR)

Package

00000000h

1300h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG3_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1308h

4

Performance Monitoring Filter Configuration (PERFCNTR3_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

130ch

4

Performance Monitoring Filter Configuration (PERFCNTR3_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1310h

4

Performance Monitoring Filter Configuration (PERFCNTR3_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1314h

4

Performance Monitoring Filter Configuration (PERFCNTR3_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1318h

4

Performance Monitoring Filter Configuration (PERFCNTR3_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1380h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP3_​0_​0_​0_​VTDBAR)

Package

00000000h

1400h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG4_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1408h

4

Performance Monitoring Filter Configuration (PERFCNTR4_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

140ch

4

Performance Monitoring Filter Configuration (PERFCNTR4_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1410h

4

Performance Monitoring Filter Configuration (PERFCNTR4_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1414h

4

Performance Monitoring Filter Configuration (PERFCNTR4_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1418h

4

Performance Monitoring Filter Configuration (PERFCNTR4_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1480h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP4_​0_​0_​0_​VTDBAR)

Package

00000000h

1500h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG5_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1508h

4

Performance Monitoring Filter Configuration (PERFCNTR5_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

150ch

4

Performance Monitoring Filter Configuration (PERFCNTR5_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1510h

4

Performance Monitoring Filter Configuration (PERFCNTR5_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1514h

4

Performance Monitoring Filter Configuration (PERFCNTR5_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1518h

4

Performance Monitoring Filter Configuration (PERFCNTR5_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1580h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP5_​0_​0_​0_​VTDBAR)

Package

00000000h

1600h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG6_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1608h

4

Performance Monitoring Filter Configuration (PERFCNTR6_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

160ch

4

Performance Monitoring Filter Configuration (PERFCNTR6_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1610h

4

Performance Monitoring Filter Configuration (PERFCNTR6_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1614h

4

Performance Monitoring Filter Configuration (PERFCNTR6_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1618h

4

Performance Monitoring Filter Configuration (PERFCNTR6_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1680h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP6_​0_​0_​0_​VTDBAR)

Package

00000000h

1700h

8

Performance Monitoring Counter Configuration (PERFCNTRCFG7_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1708h

4

Performance Monitoring Filter Configuration (PERFCNTR7_​FLTR0_​0_​0_​0_​VTDBAR)

Package

00000000h

170ch

4

Performance Monitoring Filter Configuration (PERFCNTR7_​FLTR1_​0_​0_​0_​VTDBAR)

Package

00000000h

1710h

4

Performance Monitoring Filter Configuration (PERFCNTR7_​FLTR2_​0_​0_​0_​VTDBAR)

Package

00000000h

1714h

4

Performance Monitoring Filter Configuration (PERFCNTR7_​FLTR3_​0_​0_​0_​VTDBAR)

Package

00000000h

1718h

4

Performance Monitoring Filter Configuration (PERFCNTR7_​FLTR4_​0_​0_​0_​VTDBAR)

Package

00000000h

1780h

4

Performance Monitoring Counter Capabilities (PERFCNTRCAP7_​0_​0_​0_​VTDBAR)

Package

10034001h

1784h

4

Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_​EG0_​0_​0_​0_​VTDBAR)

Package

00000005h

1e00h

8

Performance Monitoring Freeze (PERFFRZ0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

1f00h

8

Performance Monitoring Overflow Status (PERFOVFSTS0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

2000h

8

Performance Monitoring Counter (PERFCNTR0_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

3000h

8

Performance Monitoring Counter (PERFCNTR1_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

4000h

8

Performance Monitoring Counter (PERFCNTR2_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

5000h

8

Performance Monitoring Counter (PERFCNTR3_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

6000h

8

Performance Monitoring Counter (PERFCNTR4_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

7000h

8

Performance Monitoring Counter (PERFCNTR5_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

8000h

8

Performance Monitoring Counter (PERFCNTR6_​0_​0_​0_​VTDBAR)

Package

0000000000000000h

9000h

8

Performance Monitoring Counter (PERFCNTR7_​0_​0_​0_​VTDBAR)

Package

0000000000000000h
Version Register (VER_REG_0_0_0_VTDBAR)