Address Translation in VMX Operation

The architecture for VMX operation includes two features that support address translation:

• Virtual-processor identifiers (VPIDs) that manage translations of linear addresses.

  Note:

  This feature is not supported by the present extension.

• Extended page-table (EPT) mechanism that supports the virtualization of physical memory. When the EPT mechanism is used, certain physical addresses used to access memory are treated as guest-software addresses. As a result, guest-software addresses are translated by traversing a set of EPT paging structures to produce physical addresses used to access memory. This feature allows the hypervisor to gain control over the resources.