12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
FPB Capabilities Register (FPBCAPR) – Offset BA4
FPB Capabilities Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 0x0 | RO | Reserved (RSVD_M) Reserved |
26:24 | 0x0 | RW/O | FPB MEM High Vector Size Supported (FPBMEMHVECSIZES) Indicates the size of the FPB MEM High Vector implemented in hardware.
All defined Granularities are allowed for all defined vector sizes. If the FPB MEM High Decode Mechanism Supported bit is Clear, then the value in this field is undefined and must be ignored by software. |
23:19 | 0h | RO | Reserved |
18:16 | 0x0 | RW/O | FPB MEM Low Vector Size Supported (FPBMEMLVECSIZES) Indicates the size of the FPB MEM Low Vector implemented in hardware, and constrains the allowed values software is permitted to write to the FPB MEM Low Vector Start field.
If the FPB MEM Low Decode Mechanism Supported bit is Clear, then the value in this field is undefined and must be ignored by software |
15:11 | 0h | RO | Reserved |
10:8 | 0x0 | RW/O | FPB RID Vector Size Supported (FPBRIDVECSIZES) Indicates the size of the FPB RID Vector implemented in hardware, and constrains the allowed values software is permitted to write to the FPB RID Vector Granularity field.
If the FPB RID Decode Mechanism Supported bit is Clear, then the value in this field is undefined and must be ignored by software. |
7:3 | 0x0 | RO | FPB Numbers Secondary Device (FPBNSECDEV) For Upstream Ports of Switches only, this field indicates the quantity of Device Numbers associated with the Secondary Side of the Upstream Port bridge. |
2 | 0x0 | RW/O | FPB MEM High Decode Mechanism Supported (FPBMEMHS) If set, indicates that the FPB MEM High Vector mechanism is supported |
1 | 0x0 | RW/O | FPB MEM Low Decode Mechanism Supported (FPBMEMLS) If set, indicates that the FPB MEM Low Vector mechanism is supported |
0 | 0x0 | RW/O | FPB RID Decode Mechanism Supported (FPBRIDS) If set, indicates that the FPB RID Vector mechanism is supported |