Intel® Core™ Ultra 200H and 200U Series Processors for Edge Platforms

Datasheet Addendum

ID Date Version Classification
847885 03/05/2025 001 Public
Document Table of Contents
Document Table of Contents
Legal and Disclaimers Revision History Introduction Thermal Management Display Graphics Enhanced Serial Peripheral Interface (eSPI) Power Management
Legal and Disclaimers
Revision History
Introduction
Introduction Terminology Reference Documents Supported Package and Die Plan
Terminology
Reference Documents
Supported Package and Die Plan
Thermal Management
Thermal Management Introduction Intel® Core™ Ultra Processor Line Thermal and Power Specifications
Thermal Management Introduction
Intel® Core™ Ultra Processor Line Thermal and Power Specifications
Display
Pipelock Bezel Correction
Pipelock
Overview
Overview
Bezel Correction
Graphics
SRIOV Overview Introduction Hardware Interface
SRIOV Overview
Introduction
Hardware Interface
Display Output from a Virtualized Environment GuC
Display Output from a Virtualized Environment
GuC
GuC Virtual Function Communication with GuC
Virtual Function Communication with GuC
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Overview Pinlist
Functional Overview
Pinlist
Power Management
Power Management System Power Management System State G1/S3 State Transition Rules for the Processor
System Power Management
System State G1/S3
State Transition Rules for the Processor

System State G1/S3

Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut to non-critical circuits. Memory is retained, and refreshes continue. All external clocks are shut off; RTC clock and internal ring oscillator clocks are still toggling.

In S3, SLP_​S3 signal stays asserted, SLP_​S4 and SLP_​S5 are inactive until a wake occurs.

State Transition Rules for the Processor