Problem

If a PCH USB Type-C port is configured in Device Mode (or in DbC mode) and connected to an external USB 3.2 host controller, it may cause the USB port to go into a non-functional state in the following scenarios:

1. PCH resumes from S3, S4, or S5 state, the port may remain in U2.
2. Port is connected to a USB 3.2 Gen 1x1 host controller when resuming from S3, S4, S5, or G3, the port may enter into Compliance Mode or an inactive state if Compliance mode is disabled.
3. Port is connected to a USB 3.2 Gen 2x1 host controller when resuming from S3, S4, S5, or G3, the port may enter an inactive state.

Implication

PCH USB Type C port configured in Device Mode (or in DbC mode) may fail to enumerate or become unavailable.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The xHCI implements the Power Management Link Timer (PM LC Timer) Timeout value as 10 us instead of 4 us as defined by the USB 3.2 specification.

Implication

USB-IF xHCI CV TD 7.21 may report a failure. Intel has obtained a waiver for TD 7.21.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

For flash device suspend/resume opcodes, the SPI controller does not use JEDEC SFDPs 13th DWORD bits [15:0], Program Suspend Instruction and Program Resume Instruction fields. The controller only uses bits [31:16], Suspend Instruction and Resume Instruction fields, to obtain the suspend/resume opcodes.

Implication

If the SPI flash requires bits [15:0] to be different than bits [31:16], then the suspend /resume feature is not functional. In this case, system behavior varies depending on what the suspend/resume instruction is and when it is generated.

Workaround

None identified.

If a device requires bits [15:0] to be different than bits [31:16], then disable the device suspend / resume via the SPI Suspend / Resume Enable soft strap.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The Intel^® Trace Hub Pipe Line Empty bit (CSR_​MTB_​BAR, Offset 0xD4) for a given output port may be set while the Input Buffer Empty for the associated output port is not set. This will only happen when the capture Done signal is de-asserted by clearing the Force Capture Done bit (CSR_​MTB_​BAR, Offset 0xD8) is cleared or the StoreQual[0] signal is de-asserted by the Trigger Unit before the pipe line is empty, and the destination is either system memory or USB (DCI).

Implication

There may be valid trace data in the trace source input buffer which did not get sent to the destination (output port).

Workaround

None identified.

Capture Done should be cleared or de-asserted after the pipe line is empty.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The xHCI may generate an unexpected short packet event for the last transfer's Transfer Request Block (TRB) when using Non-Event Data TRB with multiples TRBs.

Implication

Transfer may fail due to the packet size error.

Workaround

None identified.

Intel recommends software to use Data Event TRBs for short packet completion.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The IOSF-SB eSPI Link Configuration Lock (SBLCL) bit (offset 4000h, bit 27 in eSPI PCR space) is reset by RSMRST# assertion instead of PLTRST# assertion.

Implication

If the SBLCL bit is set to 1, software will not be able to access the eSPI device Capabilities and Configuration register in the reserved address range (0h - 7FFh) until RSMRST# asserts.

Workaround

If software needs to access the eSPI device reserved range 0h - 7FFh while SBLCL bit is set to 1, a RSMRST# assertion should be performed.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

If USB audio offload is enabled for a USB Full-Speed Isochronous audio device connected behind a USB 2.0 or later hub and there is an active concurrent bulk transfer to another device on any port of the xHCI controller or behind the hub, the controller may stall the offloaded audio traffic and a split transaction error may occur.

Implication

The USB audio offload playback may stop. Audio may be recovered if the audio stream is paused and restarted, the audio device is removed and reconnected, or the audio application is restarted.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The xHCI spec version 1.2 defines the PCI Express Capability structure offset 04h Device Capabilities (DVSEC) field to be 8 bytes. The USB Virtualization Based Trusted IO (VTIO) Management controller implements the DVSEC field as 12 bytes.

Implication

An USB controller driver may not be able to enable the USB VTIO controller.

Workaround

None identified. To mitigate this erratum, an Independent Software Vendor could account for the field length in the USB controller driver.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller

Implication

The processor may fail to enter C3 or deeper package C-States.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The xHCI controller does not return the correct completion code for the Force Header Command as defined in the Section 4.6.16 of the eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification Rev 1.2.

Implication

xHCI CV TD4.12 - Force Header Command Test may report an error. Intel has obtained a waiver for TD 4.12. The Force Header Command is only used by the USB-IF Command Verifier (xHCI CV) tool for device testing. There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

When the VCCPRIM_​1P8 is off and the VCCPRIM_​3P3 is powered on during G3 to S5, there may be a leakage current from the VCCPRIM_​3P3 power rail to VCCPRIM_​1P8 power rail.

Implication

The leakage voltage may be observed on VCCPRIM_​1P8 power rail. There is no known functional or reliability impact.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

An invalid instruction opcode that runs into another exception before fetching all instruction bytes (example:, A #GP due to the instruction being longer than 15 bytes or a CS limit violation) may signal a #UD despite not fetching all instruction bytes under some microarchitectural conditions.

Implication

Due to this erratum, a #UD exception may be serviced before other exceptions. This does not occur for valid instructions. Intel has only observed this erratum in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

The Type-C controller does not properly support Qword accesses to its MSI-X interrupt table which may lead to unexpected behavior.

Implication

When this erratum occurs, Qword reads do not return Unsupported Request and may not return correct data and Qword writes may lead to unexpected behavior. Intel has not observed this erratum to affect any commercially available software.

Workaround

Software should not utilize Qword access for the Type-C MSI-X table.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

A microcode update initiated by writing to MSR IA32_​BIOS_​UPDT_​TRIG (MSR 79h) may cause the system to hang.

Implication

Due to this erratum, the microcode update will not complete and a system may hang with machine check exception (MSCOD = 045CH, MCACOD =0402H )

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

A microcode update initiated by writing to MSR IA32_​BIOS_​UPDT_​TRIG (MSR 79h) may cause the system to hang.

Implication

Due to this erratum, the USB Low-Speed or Full-Speed device may fail to enumerate when connected to the USB 2.0 hub. This condition is recovered after the xHCI controller has been reset (for example, software setting the xHCI Host Controller Reset (HCRST) bit or by performing a power button override).

Workaround

A BIOS code change has been identified and may be implemented as a workaround for this erratum

Status

For the steppings affected, refer to Summary Tables of Changes.

Problem

Under complex microarchitectural conditions, a read on one logical processor may not receive the most recently stored data by another logical processor.

Implication

Due to this erratum, unpredictable system behavior or a system hang may occur. Intel has only observed this behavior in a synthetic test environment. Intel has not observed this erratum with any commercially available system.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to Summary Tables of Changes.