12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID Date Version Classification
655258 28/10/2021 00:00:00 Public Content

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Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory PCIe* Interface Direct Media Interface and On Package Interface Graphics Display Signal Description Electrical Specifications Package Mechanical Specifications CPU And Device IDs
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Support Supported Technologies Power Management Support Thermal Management Support Ball-out Information Processor Testability Operating Systems Support Terminology and Special Marks Related Documents
Processor Volatility Statement
Package Support
Supported Technologies
Supported Technologies API Support (Windows*)
API Support (Windows*)
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ball-out Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Related Documents
Technologies
Technologies Platform Environmental Control Interface Intel® Virtualization Technology Security Technologies Power and Performance Technologies Debug Technologies Clock Topology Intel Volume Management Device Technology Deprecated Technologies
Platform Environmental Control Interface
Platform Environmental Control Interface PECI Bus Architecture
PECI Bus Architecture
Intel® Virtualization Technology
Intel® Virtualization Technology Intel® VT for Intel® 64 and Intel® Architecture Intel® Virtualization Technology for Directed I/O Intel® APIC Virtualization Technology (Intel® APICv) Hypervisor-Managed Linear Address Translation
Intel® VT for Intel® 64 and Intel® Architecture
Intel® Virtualization Technology for Directed I/O
Intel® APIC Virtualization Technology (Intel® APICv)
Hypervisor-Managed Linear Address Translation
Security Technologies
Security Technologies Intel® Trusted Execution Technology Intel® Advanced Encryption Standard New Instructions Perform Carry-Less Multiplication Quad Word Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection Intel® Supervisor Mode Access Protection Intel® Secure Hash Algorithm Extensions User Mode Instruction Prevention Read Processor ID Intel® Multi-Key Total Memory Encryption Intel® Control-flow Enforcement Technology KeyLocker Technology Devil’s Gate Rock
Intel® Trusted Execution Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection
Intel® Supervisor Mode Access Protection
Intel® Secure Hash Algorithm Extensions
User Mode Instruction Prevention
Read Processor ID
Intel® Multi-Key Total Memory Encryption
Intel® Control-flow Enforcement Technology
Intel® Control-flow Enforcement Technology Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
KeyLocker Technology
Devil’s Gate Rock
Power and Performance Technologies
Power and Performance Technologies Intel® Smart Cache Technology IA Cores Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Max Technology 3.0 Intel® Hyper-Threading Technology Intel® Turbo Boost Technology 2.0 Enhanced Intel SpeedStep® Technology Intel® Thermal Velocity Boost (Intel® TVB) Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology Intel® GMM and Neural Network Accelerator Cache Line Write Back Remote Action Request User Mode Wait Instructions
Intel® Smart Cache Technology
IA Cores Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Power Monitoring Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Frequency
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology
Intel® GMM and Neural Network Accelerator
Cache Line Write Back
Remote Action Request
User Mode Wait Instructions
Debug Technologies
Debug Technologies Intel® Processor Trace Platform CrashLog Telemetry Aggregator
Intel® Processor Trace
Platform CrashLog
Telemetry Aggregator
Clock Topology
Clock Topology Integrated Reference Clock PLL
Integrated Reference Clock PLL
Intel Volume Management Device Technology
Deprecated Technologies
Power Management
Power Management Advanced Configuration and Power Interface (ACPI) States Supported Processor IA Core Power Management Processor AUX Power Management Processor Graphics Power Management System Agent Enhanced Intel SpeedStep® Technology Rest Of Platform (ROP) PMIC PCI Express* Power Management TCSS Power State
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor IA Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor AUX Power Management
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
System Agent Enhanced Intel SpeedStep® Technology
Rest Of Platform (ROP) PMIC
PCI Express* Power Management
TCSS Power State
Thermal Management
Thermal Management Processor Thermal Management Processor Line Thermal and Power Specifications
Processor Thermal Management
Processor Thermal Management Thermal Considerations Assured Power (cTDP) Thermal Management Features Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Assured Power (cTDP)
Assured Power (cTDP) Assured Power (cTDP)
Assured Power (cTDP)
Thermal Management Features
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection On-Demand Mode MSR Based On-Demand Mode I/O Emulation-Based On-Demand Mode
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
Intel® Memory Thermal Management
Processor Line Thermal and Power Specifications
Processor Line Thermal and Power Specifications Processor Line Power and Frequency Specifications Processor Line Thermal and Power
Processor Line Power and Frequency Specifications
Processor Line Thermal and Power
Memory
Memory System Memory Interface Integrated Memory Controller (IMC) Power Management
System Memory Interface
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) Memory Controller Power Gate System Memory Controller Organization Mode (DDR4/5 Only) System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair (PPR)
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
System Memory Timing Support System Memory Timing Support SAGV Points DDR Frequency Shifting
System Memory Timing Support
SAGV Points
DDR Frequency Shifting
Memory Controller (MC)
Memory Controller Power Gate
System Memory Controller Organization Mode (DDR4/5 Only)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DRAM Power Management and Initialization Initialization Role of CKE Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Initialization Role of CKE
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
PCIe* Interface
PCIe* Interface Processor PCI Express* Interface
Processor PCI Express* Interface
Processor PCI Express* Interface PCI Express* Support PCI Express* Architecture PCI Express* Configuration Mechanism PCI Express* Equalization Methodology PCI Express* Hot Plug
PCI Express* Support
PCI Express* Architecture
PCI Express* Configuration Mechanism
PCI Express* Equalization Methodology
PCI Express* Hot Plug
Direct Media Interface and On Package Interface
Direct Media Interface (DMI) On Package Interface (OPI)
Direct Media Interface (DMI)
Direct Media Interface (DMI) DMI Lane Reversal and Polarity Inversion DMI Error Flow DMI Link Down
DMI Lane Reversal and Polarity Inversion
DMI Error Flow
DMI Link Down
On Package Interface (OPI)
OPI Support Functional Description
OPI Support
Functional Description
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Configuration Display Features
Display Technologies Support
Display Configuration
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
Integrated Audio
Signal Description
Signal Description System Memory Interface PCI Express* Graphics (PEG) Signals Direct Media Interface (DMI) Signals Reset and Miscellaneous Signals Display Interfaces Processor Clocking Signals Testability Signals Error and Thermal Protection Signals Power Sequencing Signals Processor Power Rails Ground and Reserved Signals Processor Internal Pull-Up / Pull-Down Terminations
System Memory Interface
System Memory Interface DDR4 Memory Interface DDR5 Memory Interface
DDR4 Memory Interface
DDR5 Memory Interface
PCI Express* Graphics (PEG) Signals
Direct Media Interface (DMI) Signals
Reset and Miscellaneous Signals
Display Interfaces
Display Interfaces Digital Display Interface (DDI) Signals Digital Display Audio Signals
Digital Display Interface (DDI) Signals
Digital Display Audio Signals
Processor Clocking Signals
Testability Signals
Error and Thermal Protection Signals
Power Sequencing Signals
Processor Power Rails
Ground and Reserved Signals
Processor Internal Pull-Up / Pull-Down Terminations
Electrical Specifications
Electrical Specifications Processor Power Rails DC Specifications
Processor Power Rails
Processor Power Rails Power and Ground Pins Voltage Regulator VCC Voltage Identification (VID)
Power and Ground Pins
Voltage Regulator
VCC Voltage Identification (VID)
DC Specifications
DC Specifications Processor Power Rails DC Specifications Processor Interfaces DC Specifications
Processor Power Rails DC Specifications
Processor Power Rails DC Specifications VCCCORE DC Specifications VccGT DC Specifications VDD2 DC Specifications Vcc1P05_PROC DC Specifications Vcc1P8_PROC DC Specifications
VCCCORE DC Specifications
VccGT DC Specifications
VDD2 DC Specifications
Vcc1P05_PROC DC Specifications
Vcc1P8_PROC DC Specifications
Processor Interfaces DC Specifications
Processor Interfaces DC Specifications DDR4 DC Specifications DDR5 DC Specifications PCI Express* Graphics (PEG) Group DC Specifications Digital Display Interface (DDI) DC Specifications CMOS DC Specifications GTL and OD DC Specification PECI DC Characteristics
DDR4 DC Specifications
DDR5 DC Specifications
PCI Express* Graphics (PEG) Group DC Specifications
Digital Display Interface (DDI) DC Specifications
CMOS DC Specifications
GTL and OD DC Specification
PECI DC Characteristics
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Storage Specifications
Package Mechanical Attributes
Package Storage Specifications
CPU And Device IDs
CPU And Device IDs CPUID PCI Configuration Header Device IDs
CPUID
PCI Configuration Header
Device IDs

Package C-States and Display Resolutions

The integrated graphics engine has the frame buffer located in system memory. When the display is updated, the graphics engine fetches display data from system memory. Different screen resolutions and refresh rates have different memory latency requirements. These requirements may limit the deepest Package C-state the processor can enter. Other elements that may affect the deepest Package C-state available are the following:

  • Display is on or off
  • Single or multiple displays
  • Native or non-native resolution
  • Panel Self Refresh (PSR) technology

Note:Display resolution is not the only factor influencing the deepest Package C-state the processor can get into. Device latencies, interrupt response latencies, and core C-states are among other factors that influence the final package C-state the processor can enter.

The following table lists display resolutions and deepest available package C-State.The display resolutions are examples using common values for blanking and pixel rate. Actual results will vary. The table shows the deepest possible Package C-state.System workload, system idle, and AC or DC power also affect the deepest possible Package C-state.

Deepest Package C-State Available

S 8+8 Processor line

Resolution

Number of Displays

PSR Enabled

PSR Disabled

Up to 5120x3200 60Hz3

Single

PC10

PC8

Notes:
  1. All Deep states are with Display ON.
  2. The deepest C-state has variance, dependent various parameters such SW and Platform devices.
  3. Partial data based on Pre-Silicon estimation.
Processor AUX Power Management