7 | 0b | RW/1L | BIOS Interface Lock-Down (BILD) When set, prevents BC.TS and BC.BBS from being changed. This bit can only be written from 0 to 1 once. BIOS Note: This bit is not backed up in the RTC well. This bit should also be set in the BUC register in the RTC device to record the last state of this value following a cold reset. |
6 | 0b | RW/L | Boot BIOS Destination (BBS) This field determines the destination of accesses to the BIOS memory range. For the default, Functional Strap section of Signal Description chapter for details. 0: SPI 1: LPC When SPI or LPC is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down is not set. |
5 | 1b | RW/L | Enable InSMM.STS (EISS) When this bit is set, the BIOS region is not writable until SMM sets the InSMM.STS bit. Today BIOS Flash is writable if WPD is a 1. If this bit [5] is set, then WPD must be a 1 and InSMM.STS (0xFED3_0880[0]) must be 1 also. If this bit [5] is clear, then BIOS is writable based only on WPD = 1 and the InSMM.STS is a dont care. |
4 | 0b | RO | Top Swap (TS) When set, PCH will invert either A16, A17, A18, A19 or A20 for cycles going to the BIOS space (but not the feature space). When cleared, PCH will not invert the lines. If booting from LPC (FWH), then the Boot Blook size is 64KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the BOOT_BLOCK_SIZE soft strap determines if A16, A17, A18, A19 or A20 should be inverted if Top Swap is enabled. If PCH is strapped for Top-Swap is low at rising edge of PWROK, then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted.
BIOS Note: 1) This bit provides a read-only path to view the state of the Top Swap strap. It is backed up and driven from the RTC well. Bios will need to program the corresponding register in the RTC Controller (in RTC well), which will be reflected in this register. 2) The Register portion of the Top Swap is lockable by the Bios Interface Lockdown Bit (BC.BILD) |
3:2 | - | - | Reserved |
1 | 0b | RW/1L | Lock Enable (LE) When set, setting the WP bit will cause SMI. When cleared, setting the WP bit will not cause SMI. Once set, this bit can only be cleared by a PLTRST#. When this bit is set, EISS - bit [5] of this register is locked down. |
0 | 0b | RW | Write Protect Disable (WPD) When set, access to the BIOS space is enabled for both read and write cycles to BIOS. When cleared, only read cycles are permitted to the FWH or SPI flash. When this bit is written from a 0 to a 1 and the LE bit is also set, an SMI# is generated. This ensures that only SMM code can update BIOS. |