eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA) – Offset 4004 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA) – Offset 4004

Along with SLV_CFG_REG_CTL, this register controls Rd/Wr access to Slave Configuration registers using eSPI Get/Set_Configuration cycles. It allows access to Slave configuration registers from Host/CSME software/firmware.

For writes (SCRT = 2'b01) to Slave Configuration registers, this register should be written to first with the required data before writing to the CTL register. The eSPI-MC processes the write to the Slave using an eSPI Set_Configuration command.

If a write is to a supported register in the reserved register address range (0h 7FFh), the eSPI-MC updates its local copy of the Slave configuration registers after the write has been successfully sent to the Slave.

Note: eSPI-MC does no checking of the register values (even for supported Slave Capabilities / Configuration Registers) the SW assumes full responsibility for programming legal values supported by both the eSPI-MC and the Slave.

For reads (SCRT = 2'b00 or 2b10) to Slave Configuration registers, the hardware writes the data read back from the Slave into this register. The read data is valid after hardware has cleared the SCRE bit in the CTL register and the SCRS field indicates a successful transaction.

Bit Range	Default	Access	Field Name and Description
31:0	0b	RW/V	Slave Configuration Register for Read and Write data (SCRD) Configuration register Write data from software or read data from the Slave. For writes, this register must be programmed before the CTL register. For reads, data in this register is valid after the CTL.SCRE bit has been cleared by HWand the CTL.SCRS field indicates a successful transaction.

Bit Range

Default

Access

Field Name and Description

31:0

RW/V

Slave Configuration Register for Read and Write data (SCRD)

Configuration register Write data from software or read data from the Slave.

For writes, this register must be programmed before the CTL register.

For reads, data in this register is valid after the CTL.SCRE bit has been cleared by HWand the CTL.SCRS field indicates a successful transaction.

Peripheral Channel Error for Slave 0 (PCERR_SLV0)

eSPI Slave Configuration Register And Link Control (SLV_CFG_REG_CTL) Peripheral Channel Error for Slave 0 (PCERR_SLV0)