Force Event Register for Error Interrupt Status (forceeventforerrintsts) – Offset 52 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
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xDCI MMIO Device
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xHCI Configuration
xHCI Memory Mapped

Force Event Register for Error Interrupt Status (forceeventforerrintsts) – Offset 52

Bit Range	Default	Access	Field Name and Description
14:11	-	-	Reserved
10	0h	WO	Force Event for Tuning Error (forcetuningerr) 1 – Interrupt is generated 0 – No Interrupt
9	0h	WO	Force Event for ADMA (forceadmaerr) 1 – Interrupt is generated 0 – No Interrupt
8	0h	WO	Force Event for Auto CMD Error (forceautocmderr) 1 – Interrupt is generated 0 – No Interrupt
7	0h	WO	Force Event for Current Limit (forcecurrlimerr) 1 – Interrupt is generated 0 – No Interrupt
6	0h	WO	Force Event for Data End Bit Error (forcedatendbiterr) 1 – Interrupt is generated 0 – No Interrupt
5	0h	WO	Force Event for Data CRC Error (forcedatcrcerr) 1 – Interrupt is generated 0 – No Interrupt
4	0h	WO	Force Event for Data Timeout Error (forcedattimeouterr) 1 – Interrupt is generated 0 – No Interrupt
3	0h	WO	Force Event for Command Index Error (forcecmdindexerr) 1 – Interrupt is generated 0 – No Interrupt
2	0h	WO	Force Event for Command End Bit Error (forcecmdendbiterr) 1 – Interrupt is generated 0 – No Interrupt
1	0h	WO	Force Event for Command CRC Error (forcecmdcrcerr) 1 – Interrupt is generated 0 – No Interrupt
0	0h	WO	Force Event for CMD Timeout Error (forcecmdtimeouterr) 1 – Interrupt is generated 0 – No Interrupt

ADMA Error Status (admaerrsts)

Force Event Register for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus) ADMA Error Status (admaerrsts)