GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0) – Offset 140 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0) – Offset 140

Bit Range	Default	Access	Field Name and Description
30:24	-	-	Reserved
23	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_23) Applied to GPP_D23. Same description as bit 0.
22	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_22) Applied to GPP_D22. Same description as bit 0.
21	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_21) Applied to GPP_D21. Same description as bit 0.
20	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_20) Applied to GPP_D20. Same description as bit 0.
19	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_19) Applied to GPP_D19. Same description as bit 0.
18	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_18) Applied to GPP_D18. Same description as bit 0.
17	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_17) Applied to GPP_D17. Same description as bit 0.
16	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_16) Applied to GPP_D16. Same description as bit 0.
15	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_15) Applied to GPP_D15. Same description as bit 0.
14	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_14) Applied to GPP_D14. Same description as bit 0.
13	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_13) Applied to GPP_D13. Same description as bit 0.
12	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_12) Applied to GPP_D12. Same description as bit 0.
11	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_11) Applied to GPP_D11. Same description as bit 0.
10	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_10) Applied to GPP_D10. Same description as bit 0.
9	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_9) Applied to GPP_D9. Same description as bit 0.
8	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_8) Applied to GPP_D8. Same description as bit 0.
7	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_7) Applied to GPP_D7. Same description as bit 0.
6	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_6) Applied to GPP_D6. Same description as bit 0.
5	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_5) Applied to GPP_D5. Same description as bit 0.
4	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_4) Applied to GPP_D4. Same description as bit 0.
3	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_3) Applied to GPP_D3. Same description as bit 0.
2	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_2) Applied to GPP_D2. Same description as bit 0.
1	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_1) Applied to GPP_D1. Same description as bit 0.
0	0b	RW/1C	GPI General Purpose Events Status (GPI_GPE_STS_GPPC_D_0) These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). If the correspondingenable bit is set in the GPI_GPE_EN register, then when the GPI_GPE_STS bit is set: - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for thecorresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.