Source Status (SSTAT0) – Offset 820 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Source Status (SSTAT0) – Offset 820

NOTE: SSTAT0 is for DMA Channel 0. The same register definition, SSTAT1, is available for Channel 1 at address 878h.

SSTAT0 (CH0): offset 820h

SSTAT1 (CH1): offset 878h

After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register. This status information is then stored in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block.

Note : This register is a temporary placeholder for the source status information on its way to the SSTATx register location of the LLI. The source status information should be retrieved by software from the SSTATx register location of the LLI, and not by a read of this register over the DMA slave interface.

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	Source Status (SSTAT) Source status information retrieved by hardware from the address pointed to by the contents of the Source Status Address Register. This register is a temporary placeholder for the source status information on its way to the SSTATn register location of the LLI. The source status information should be retrieved by software from the SSTATn register location of the LLI, and not by a read of this register over the DMA slave interface.

Bit Range

Default

Access

Field Name and Description

31:0

Source Status (SSTAT)

Source status information retrieved by hardware from the address pointed

to by the contents of the Source Status Address Register.

This register is a temporary placeholder for the source status information

on its way to the SSTATn register location of the LLI.

The source status information should be retrieved by software from the SSTATn

register location of the LLI, and not by a read of this register over the

DMA slave interface.

Destination Status (DSTAT0)

Control Register High (CTL_HI0) Destination Status (DSTAT0)