Intel® Core™ Ultra Processors for H-series and U-series Platforms CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795258 | 07/29/2024 | Public |
Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 3)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1)
Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_PCU)
Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_PCU)
P-State Limits (P_STATE_LIMITS_0_2_0_GTTMMADR)
Plane Turbo Performance BIAS (GT_IA_PERF_BIAS_0_2_0_GTTMMADR)
Secondare Plane Turbo Power Policy (SECP_TURBO_PLCY_0_2_0_GTTMMADR)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2)
(RP_STATE_CAP_0_0_0_PCU)
Ratio Sum of Active GT (PKG_GCD_C0_ANY_RATIO_0_2_0_GTTMMADR)
Package GCD C0 EUs SUM (PKG_GCD_C0_EUS_SUM_0_2_0_GTTMMADR)
Cycle Sum of Any Active Media (PKG_MEDIA_C0_ANY_SLICE_0_2_0_GTTMMADR)
Cycle Sum of All Active Media (PKG_MEDIA_C0_SLICES_SUM_0_2_0_GTTMMADR)
Ratio Sum of Active Media (PKG_MEDIA_C0_ANY_RATIO_0_2_0_GTTMMADR)
Ratio Sum of Active Media Slice (PKG_MEDIA_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR)
Package Media C0 EUs SUM (PKG_MEDIA_C0_EUS_SUM_0_2_0_GTTMMADR)
Ratio Sum of Active GCD Slice (PKG_GCD_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR)
Cycle Sum of Active Media (PKG_MEDIA_C0_ANY_0_2_0_GTTMMADR)
Cycle Sum of Active Graphics (PKG_GCD_C0_ANY_0_2_0_GTTMMADR)
Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_2_0_GTTMMADR)
Cycle Sum of Any Active GT Slice (PKG_GCD_C0_ANY_SLICE_0_2_0_GTTMMADR)
Cycle Sum of All Active GT Slice (PKG_GCD_C0_SLICES_SUM_0_2_0_GTTMMADR)
Thermal Status GT (THERM_STATUS_GT_0_2_0_GTTMMADR)
GT Thermal Interrupt (THERM_INTERRUPT_GT_0_2_0_GTTMMADR)
PCU Reference Clock (PCU_REFERENCE_CLOCK_0_2_0_GTTMMADR)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
Vendor ID (VID_0_0_0_PCI)
Device ID (DID_0_0_0_PCI)
PCI Command (PCICMD_0_0_0_PCI)
PCI Status (PCISTS_0_0_0_PCI)
Revision ID (RID_0_0_0_PCI)
Class Code Programming Interface (CC_PI_0_0_0_PCI)
Basic Class Code (CC_BCC_0_0_0_PCI)
Header Type (HDR_0_0_0_PCI)
Subsystem Vendor Identification (SVID_0_0_0_PCI)
Subsystem Identification (SID_0_0_0_PCI)
Capabilities Pointer (CAPPTR_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
MCHBAR Base Address Register (MCHBAR_0_0_0_PCI)
Graphics Control (GGC_0_0_0_PCI)
Device Enable (DEVEN_0_0_0_PCI)
Protected Audio Video Path Control (PAVPC_0_0_0_PCI)
DMA Protected Range (DPR_0_0_0_PCI)
PCIEXBAR Base Address Register (PCIEXBAR_0_0_0_PCI)
DMIBAR Base Address Register (DMIBAR_0_0_0_PCI)
Programmable Attribute Map 0 (PAM0_0_0_0_PCI)
Programmable Attribute Map 1 (PAM1_0_0_0_PCI)
Programmable Attribute Map 2 (PAM2_0_0_0_PCI)
Programmable Attribute Map 3 (PAM3_0_0_0_PCI)
Programmable Attribute Map 4 (PAM4_0_0_0_PCI)
Programmable Attribute Map 5 (PAM5_0_0_0_PCI)
Programmable Attribute Map 6 (PAM6_0_0_0_PCI)
Legacy Access Control (LAC_0_0_0_PCI)
Top of Memory (TOM_0_0_0_PCI)
Top of Upper Usable DRAM (TOUUD_0_0_0_PCI)
Base Data of Stolen Memory (BDSM_0_0_0_PCI)
Base of GTT Stolen Memory (BGSM_0_0_0_PCI)
TSEG Memory Base (TSEGMB_0_0_0_PCI)
Top of Low Usable DRAM (TOLUD_0_0_0_PCI)
Scratchpad Data (SKPD_0_0_0_PCI)
Capabilities A (CAPID0_A_0_0_0_PCI)
Capabilities B (CAPID0_B_0_0_0_PCI)
Capabilities C (CAPID0_C_0_0_0_PCI)
Capabilities E (CAPID0_E_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
MemSS PMA BIOS memory configuration register (MEMSS_PMA_CR_BIOS_MEM_CONFIG)
MemSS PMA memory configuration register (MEMSS_PMA_CR_MEM_CONFIG)
MemSS PMA BIOS request register (MEMSS_PMA_CR_BIOS_REQ)
MemSS PMA init state register (MEMSS_PMA_CR_INIT_STATE)
MemSS PMA BIOS data register (MEMSS_PMA_CR_BIOS_DATA)
MemSS PMA BIOS mailbox register (MEMSS_PMA_CR_BIOS_MAILBOX)
MemSS PMA BIOS error status register (MEMSS_PMA_CR_BIOS_ERROR_STATUS)
BIOS MRC Revision (MEMSS_PMA_CR_MRC_VERSION)
Countdown Timer (MEMSS_PMA_CR_COUNTDOWN_TIMER)
Counter increments by 1 every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Lo)
Counter increments by overflow value of PKG_MC_C0_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Hi)
Counter increments by CMI PLL ratio every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Lo)
Counter increments by overflow value of PKG_MC_C0_RATIO_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Hi)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
Inter-Channel Decode Parameters (MAD_INTER_CHANNEL_0_0_0_MCHBAR)
Intra-Channel 0 Decode Parameters (MAD_INTRA_CH0_0_0_0_MCHBAR)
Intra-Channel 1 Decode Parameters (MAD_INTRA_CH1_0_0_0_MCHBAR)
Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR)
Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR)
Opportunistic self refresh idle timer register (PM_OPP_SREF_IDLE_TIMER_0_0_0_MCHBAR)
Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR)
RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)
Read Occupancy Count (READ_OCCUPANCY_COUNT_0_0_0_MCHBAR)
Address Compare for ECC Error Inject (ECC_Inj_Addr_Compare_0_0_0_MCHBAR)
Remap Base (REMAPBASE_0_0_0_MCHBAR)
Remap Limit (REMAPLIMIT_0_0_0_MCHBAR)
WrCAS Counter (PWM_WRCAS_COUNT_0_0_0_MCHBAR)
PWM NON SR COUNT 0 0 0 MCHBAR (PWM_NON_SR_COUNT_0_0_0_MCHBAR)
PWM ACT COUNT 0 0 0 MCHBAR (PWM_ACT_COUNT_0_0_0_MCHBAR)
Address Mask for ECC Error Inject (ECC_Inj_Addr_Mask_0_0_0_MCHBAR)
PMON GLOBAL CONTROL 0 0 0 MCHBAR (PMON_GLOBAL_CONTROL_0_0_0_MCHBAR)
PMON UNIT CONTROL 0 0 0 MCHBAR (PMON_UNIT_CONTROL_0_0_0_MCHBAR)
PMON GLOBAL STATUS 0 0 0 MCHBAR (PMON_GLOBAL_STATUS_0_0_0_MCHBAR)
PMON UNIT STATUS 0 0 0 MCHBAR (PMON_UNIT_STATUS_0_0_0_MCHBAR)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR[0])
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR[0])
OS Telemetry Control (OS_TELEMETRY_CONTROL_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
PRE Command Timing (TC_PRE_0_0_0_MCHBAR)
RD to RD Timings (TC_RDRD_0_0_0_MCHBAR)
RD to WR Timings (TC_RDWR_0_0_0_MCHBAR)
WR to RD Timings (TC_WRRD_0_0_0_MCHBAR)
WR to WR Timings (TC_WRWR_0_0_0_MCHBAR)
Roundtrip Latency (SC_Roundtrip_latency_0_0_0_MCHBAR)
ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR)
ECC Error Log 1 (ECCERRLOG1_0_0_0_MCHBAR)
Power Down Timing (TC_PWRDN_0_0_0_MCHBAR)
CAS Timing (TC_CAS_0_0_0_MCHBAR)
ODT Matrix (SC_ODT_MATRIX_0_0_0_MCHBAR)
Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR)
WCK Timing (TC_WCK_0_0_0_MCHBAR)
ACT Command Timing (TC_ACT_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
TC REFm 0 0 0 MCHBAR (TC_REFm_0_0_0_MCHBAR)
Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
Refresh Parameters (RFP_0_0_0_MCHBAR)
ZQCAL Control (TC_ZQCAL_0_0_0_MCHBAR)
Miscellaneous MR (TC_MR_0_0_0_MCHBAR)
Refresh Timing Parameters (TC_RFTP_0_0_0_MCHBAR)
Self-Refresh Exit Timing Parameters (TC_SREXITTP_0_0_0_MCHBAR)
Read/Write Retraining (TC_RETRAINING_OSCL_0_0_0_MCHBAR)
ECC Inject Count (ECC_Inject_count_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1)
BIOS POST Code (BIOS_POST_CODE_0_0_0_MCHBAR_PCU)
(DDR_PTM_CTL_0_0_0_MCHBAR_PCU)
Package RAPL Performance Status (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU)
GT IA Performance BIAS (GT_IA_PERF_BIAS_0_0_0_MCHBAR_PCU)
Secondary Plane Turbo Policy (SECP_TURBO_PLCY_0_0_0_MCHBAR_PCU)
Primary Plane Energy Status (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU)
Secondary Plane Energy Status (SECP_NRG_STTS_0_0_0_MCHBAR_PCU)
Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU)
Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU)
Primary Plane 0 Temperature (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU)
RP-State Limits (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU)
Package Power Limit (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU)
Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU)
BIOS Mailbox Data (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU)
BIOS Mailbox Interface (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU)
BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU)
Configurable TDP Nominal (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU)
Configurable TDP Level 1 (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU)
Configurable TDP Level 2 (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU)
Configurable TDP Control (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU)
Turbo Activation Ratio (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU)
Overclocking Status (OC_STATUS_0_0_0_MCHBAR_PCU)
Base Clock (BCLK) Frequency (BCLK_FREQ_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2)
Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU)
Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active GT and Core (PKG_GT_AND_IA_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active GT and Core (DMU_IA_GT_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Overlapping Active Media and Core (DMU_IA_MEDIA_OVERLAP_0_0_0_MCHBAR_PCU)
Cycle Sum of Any Active Core (CDIE_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU)
IA Performance Limit Reasons (IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR_PCU)
GT Performance Limit Reasons (GT_PERF_LIMIT_REASONS_0_0_0_MCHBAR_PCU)
System Agent Performance Status (SA_PERF_STATUS_0_0_0_MCHBAR_PCU)
GT Performance Status (GT_PERF_STATUS_0_0_0_MCHBAR_PCU)
Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU)
RP-State Capability (RP_STATE_CAP_0_0_0_MCHBAR_PCU)
Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU)
Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU)
Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU)
(CORE_PERF_MIN_MAX_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
Version Register (VER_REG_0_0_0_VTDBAR)
Capability Register (CAP_REG_0_0_0_VTDBAR)
Extended Capability Register (ECAP_REG_0_0_0_VTDBAR)
Global Command Register (GCMD_REG_0_0_0_VTDBAR)
General Status Register (GSTS_REG_0_0_0_VTDBAR)
Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR)
Context Command Register (CCMD_REG_0_0_0_VTDBAR)
Fault Status Register (FSTS_REG_0_0_0_VTDBAR)
Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR)
Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR)
Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR)
Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR)
Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR)
Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR)
Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR)
Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR)
Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR)
Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR)
Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR)
Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR)
Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR)
Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR)
Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR)
Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR)
Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR)
Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR)
IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR)
Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR)
Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR)
Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR)
Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR)
Page Request Status Register (PRS_REG_0_0_0_VTDBAR)
Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR)
Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR)
Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR)
Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR)
MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR)
MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR)
Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR)
Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR)
Enhanced Command (ECMD_0_0_0_VTDBAR)
Enhanced Command Response (ERESP_0_0_0_VTDBAR)
Enhanced Command Status (ESTS0_0_0_0_VTDBAR)
Enhanced Command Status (ESTS1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP0_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP2_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR)
Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR)
Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR)
Invalidate Address Register (IVA_REG_0_0_0_VTDBAR)
IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
D10:F0 Platform Monitoring Technology (PMT) Registers
Device ID and Vendor ID (VENDOR_ID_DEVICE_ID)
Command and Status (COMMAND_STATUS)
Revision ID and Class Code (REVISION_ID)
Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE)
Base Address (PM_BAR)
Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID)
Capabilities Pointer (CAPABILITIES_POINTER)
Interrupt line (INTERRUPT_LINE)
PCIe Capability ID (PCIE_CAPID)
Device Capabilities (DEV_CAP)
PCIE Device Control and Status (DEV_CTL_STS)
Power Management Capabilities (PM_CAPID)
Power Management Control Status (PM_CONTROL_STATUS)
Telemetry Capability Header (TELEM_CAPABILITY_HEADER)
Telemetry VSEC 0 (TELEM_VSEC_0)
Telemetry VSEC 1 (TELEM_VSEC_1)
Telemetry VSEC 2 (TELEM_VSEC_2)
Watcher Capability Header (WATCHER_CAPABILITY_HEADER)
Watcher VSEC 0 (WATCHER_VSEC_0)
Watcher VSEC 1 (WATCHER_VSEC_1)
Watcher VSEC 2 (WATCHER_VSEC_2)
Crashlog Capability Header (CRASHLOG_CAPABILITY_HEADER)
Crashlog VSEC 0 (CRASHLOG_VSEC_0)
Crashlog VSEC 1 (CRASHLOG_VSEC_1)
Crashlog VSEC 2 (CRASHLOG_VSEC_2)
D11:F0 Vision Processing Unit
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Base Address Register (BAR2)
Base Address Register High (BAR2_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
PCIe Capabilities (PCIECAPREG)
PCIe Device Capability (DEVCAPREG)
PCIe Device Control Status (DEVCTRLSTAT)
PCIe Device Capability2 (DEVCAPREG2)
PCIe Device Control2 Status (DEVCTRLSTAT2)
Power Management Capability ID (POWERCAPID)
Power Management Control And Status (PMECTRLSTATUS)
PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG)
Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_PCI_REGRW1)
General Purpose Read Write 2 (GEN_PCI_REGRW2)
General Purpose Read Write 3 (GEN_PCI_REGRW3)
General Purpose Read Write 4 (GEN_PCI_REGRW4)
General Purpose Input (GEN_INPUT_REG)
Msix Capability (MSIX_CAP_REG)
MSIX Table Pointer (MSIX_TABLE_PTR)
MSIX PBA Pointer (MSIX_PBA_PTR)
MSI Capability (MSI_CAP_REG)
MSI Message Low Address (MSI_ADDR_LOW)
MSI Message High Address (MSI_ADDR_HIGH)
MSI Message Data (MSI_MSG_DATA)
MSI Mask (MSI_MASK)
MSI Pending (MSI_PENDING)
VTDBAR Base Low Address (VTDBAR_LOW)
VTdBAR Base High Address (VTDBAR_HIGH)
Manufacturers ID (MANID)
ATS Extended Capability Header (ATS_EXT_CAP_HEAD)
ATS Capability and Control (ATS_CAP_CONTROL_HEAD)
SRIOV PCIE Capability (SRIOV_PCIE_CAP_ID)
SRIOV Capability (SRIOV_CAP)
SRIOV Control And Status (SRIOV_CTRL_STATUS)
Initial and Total VF (TOT_INIT_VF)
NUMVF And Function Dependency Link (NUMVF_SRIOV_FUN_DEP_LINK)
VF Offset Stride (VF_OFFSET_STRIDE)
VF Device ID (VF_DEVICE_ID)
SRIOV Supported Page Size (SRIOV_SUP_PAGE_SIZE)
SRIOV System Page Size (SRIOV_SYSTEM_PAGE_SIZE)
VF Base Address Low (VF_BASE_ADDR_REG_LOW)
VF Base Address High (VF_BASE_ADDR_REG_HI)
VF Migration Array (VF_MIGRATION_ARRAY)
D14:F0 Volume Management Device
Vendor ID (VID_0_14_0_PCI)
Device ID (DID_0_14_0_PCI)
PCI Command (PCICMD_0_14_0_PCI)
PCI Status (PCISTS_0_14_0_PCI)
Revision ID (RID_0_14_0_PCI)
Class Code (CCRIF_0_14_0_PCI)
Class Code Register Classes (CCRC_0_14_0_PCI)
Cache Line Size (CLSR_0_14_0_PCI)
Header Type (HDR_0_14_0_PCI)
VMD Configuration Base Address (CFGBAR_0_14_0_PCI)
VMD Memory Base Address Range 1 (MEMBAR1_0_14_0_PCI)
VMD Memory Base Address Range 2 (MEMBAR2_0_14_0_PCI)
Subsystem Vendor ID (SVID_0_14_0_PCI)
Subsystem ID (SSID_0_14_0_PCI)
Capabilities Pointer (CAPPTR_0_14_0_PCI)
Interrupt Line Register (INTL_0_14_0_PCI)
Interrupt Pin Register (INTPIN_0_14_0_PCI)
VMCAP (VMCAP_0_14_0_PCI)
Volume Management Configuration (VMCONFIG_0_14_0_PCI)
VMASSIGN (VMASSIGN_0_14_0_PCI)
MEMBAR1SZ (MEMBAR1SZ_0_14_0_PCI)
MEMBARxSZ Bits (MEMBAR2SZ_0_14_0_PCI)
ROOTBUS (ROOTBUS_0_14_0_PCI)
FNx_ASSIGN (FN0_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN1_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN2_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN3_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN4_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN5_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN6_ASSIGN_0_14_0_PCI)
FNx_ASSIGN (FN7_ASSIGN_0_14_0_PCI)
D2:F0 Processor Graphics
Vendor Identification (VID2_0_2_0_PCI)
Device Identification (DID2_0_2_0_PCI)
PCI Command (PCICMD_0_2_0_PCI)
PCI Status (PCISTS2_0_2_0_PCI)
Revision Identification and Class Code register (RID2_CC_0_2_0_PCI)
Cache Line Size (CLS_0_2_0_PCI)
Master Latency Timer (MLT2_0_2_0_PCI)
Header Type (HDR2_0_2_0_PCI)
Built In Self Test (BIST_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI)
Local Memory Bar (LMEMBAR0_0_2_0_PCI)
Local Memory Bar (LMEMBAR1_0_2_0_PCI)
Subsystem Vendor Identification (SVID2_0_2_0_PCI)
Subsystem Identification (SID2_0_2_0_PCI)
Capabilities Pointer (CAPPOINT_0_2_0_PCI)
Interrupt Line (INTRLINE_0_2_0_PCI)
Interrupt Pin (INTRPIN_0_2_0_PCI)
Minimum Grant (MINGNT_0_2_0_PCI)
Maximum Latency (MAXLAT_0_2_0_PCI)
Capability Identifier (CAPID0_0_2_0_PCI)
Capabilities Control (CAPCTRL0_0_2_0_PCI)
Capabilities A (CAPID0_A_0_2_0_PCI)
Capabilities B (CAPID0_B_0_2_0_PCI)
PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI)
Device 2 Control (DEV2CTL_0_2_0_PCI)
VTd Status (VTD_STATUS_0_2_0_PCI)
PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI)
PCI Express Capability (PCIECAP_0_2_0_PCI)
Device Capabilities (DEVICECAP_0_2_0_PCI)
PCI Express Device Control (DEVICECTL_0_2_0_PCI)
PCI Express Device Status Register (DEVICESTS_0_2_0_PCI)
Link Capabilities (LINKCAP_0_2_0_PCI)
Link Control and Status (LINKCTRLSTS_0_2_0_PCI)
Device Capabilities 2 (DEVCAP2_0_2_0_PCI)
Device Control 2 (DEVCTRL2_0_2_0_PCI)
Link Capabilities 2 (LINKCAP2_0_2_0_PCI)
Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI)
Message Control (MC_0_2_0_PCI)
Message Address (MA0_0_2_0_PCI)
Message Address (MA1_0_2_0_PCI)
Message Data (MD_0_2_0_PCI)
MSI Mask Bits (MSI_MASK_0_2_0_PCI)
MSI Pending Bits (MSI_PEND_0_2_0_PCI)
Power Management Capabilities ID (PMCAPID_0_2_0_PCI)
Power Management Capabilities (PMCAP_0_2_0_PCI)
Power Management Control and Status (PMCS_0_2_0_PCI)
Graphics System Event (GSE_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI)
Stepping Revision ID (SRID_0_2_0_PCI)
ASL Storage (ASLS_0_2_0_PCI)
ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI)
ARI Capability (ARI_CAP_0_2_0_PCI)
ARI Control (ARI_CTRL_0_2_0_PCI)
PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI)
PASID Capability (PASID_CAP_0_2_0_PCI)
PASID Control (PASID_CTRL_0_2_0_PCI)
ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI)
ATS Capability (ATS_CAP_0_2_0_PCI)
ATS Control (ATS_CTRL_0_2_0_PCI)
Page Request Extended Capability Header (PR_EXTCAP_0_2_0_PCI)
Page Request Control (PR_CTRL_0_2_0_PCI)
Page Request Status (PR_STATUS_0_2_0_PCI)
Outstanding Page Request Capacity (OPRC_0_2_0_PCI)
Outstanding Page Request Allocation (OPRA_0_2_0_PCI)
SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI)
SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI)
SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI)
SRIOV Status (SRIOV_STS_0_2_0_PCI)
SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI)
SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI)
Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI)
First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI)
VF Stride (VF_STRIDE_0_2_0_PCI)
VF Device ID (VF_DEVICEID_0_2_0_PCI)
Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI)
System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI)
VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI)
VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI)
VF Migration State Array Offset (VF_MIGST_OFFSET_0_2_0_PCI)
LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI)
Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI)
Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI)
PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI)
PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI)
PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)
D4:F0 Dynamic Tuning Technology
Vendor ID (VID_0_4_0_PCI)
Device ID (DID_0_4_0_PCI)
PCI Command (PCICMD_0_4_0_PCI)
PCI Status (PCISTS_0_4_0_PCI)
Revision ID (RID_0_4_0_PCI)
Class Code (CC_0_4_0_PCI)
Extended Class Code (CC_0_4_0_NOPI_PCI)
Cache Line Size (CLS_0_4_0_PCI)
Master Latency Timer (MLT_0_4_0_PCI)
Header Type (HDR_0_4_0_PCI)
Built In Self Test (BIST_0_4_0_PCI)
Thermal Controller Base Address (TMBAR_0_4_0_PCI)
Subsystem Vendor ID (SVID_0_4_0_PCI)
Subsystem ID (SID_0_4_0_PCI)
Capabilities Pointer (CAPPOINT_0_4_0_PCI)
Interrupt Line Register (INTRLINE_0_4_0_PCI)
Interrupt Pin Register (INTRPIN_0_4_0_PCI)
Minimum Guaranteed (MINGNT_0_4_0_PCI)
Maximum Latency (MAXLAT_0_4_0_PCI)
Device Enable (DEVEN_0_4_0_PCI)
Capabilities A (CAPID0_A_0_4_0_PCI)
Capabilities B (CAPID0_B_0_4_0_PCI)
D5:F0 Image Processing Unit
Vendor ID and Device ID (VID_DID)
Command and Status (PCICMD_PCISTS)
Revision ID and Class Code (RID_CC)
Cache Line Size, Master Latency Timer, Header Type and BIST (CLS_MLT_HT_BIST)
IPU BAR LOW (ISPMMADR_LOW)
IPU BAR HIGH (ISPMMADR_HIGH)
Subsystem Vendor ID and Subsystem ID (SVID_SID)
Capabilities Pointer (CAPPOINT)
Interrupt Properties (INTR)
PCIe Capabilities (PCIECAPHDR_PCIECAP)
Device Capabilities (DEVICECAP)
Device Capabilities and Control (DEVICECTL_DEVICESTS)
MSI Capabilities and MSI Control (MSI_CAPID)
MSI Address Low (MSI_ADDRESS_LO)
MSI Address High (MSI_ADDRESS_HI)
MSI Data (MSI_DATA)
Power Management Capabilities (PMCAP)
Power Management Control and Status (PMCS)
ATS Extended Capabiilty (ATSEXTCAP)
ATS Capabiilty and Control (ATSCAPCTL)
PCI Status (PCISTS_0_14_0_PCI) – Offset 6
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant Master Abort (MA) and PCI compliant Target Abort (TA).
PCISTS also indicates the DEVSEL# timing that has been set by the VMD.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 15 | 0h | RO | Detected Parity Error (DPE) Not used by VMD. |
| 14 | 0h | RO | Signaled System Error (SSE) Not used by VMD. |
| 13 | 0h | RO | Received Master Abort (RMA) Not used by VMD. |
| 12 | 0h | RO | Received Target Abort (RTA) Not used by VMD. |
| 11 | 0h | RO | Signaled Target Abort (STA) Not used by VMD. |
| 10:9 | 0h | RO | DEVSEL# Timing Status (DEVSEL_Timing) Not applicable to PCI Express. Hardwired to 0. |
| 8 | 0h | RO | Master Data Parity Error Detected (MDPE) Not used by VMD. |
| 7 | 0h | RO | Fast Back to Back Capable (Fast_Back_To_Back) Not applicable to VMD. Hardwired to 0. |
| 6 | 0h | RO | Reserved |
| 5 | 0h | RO | Primary 66 MHz Capable (pci66MHz_capable) Not applicable to VMD. Hardwired to 0. |
| 4 | 1h | RO | Capabilities List (Capabilities_List) This bit indicates the presence of a capabilities list structure. |
| 3 | 0h | RO | Interrupt Status (INTx_Status) Indicates a pending INTx interrupt. Not used by VMD. |
| 2:0 | 0h | RO | Reserved |