32-bit Base Address Register (BAR) – Offset 10 - 001 - ID:834823 | Intel® Core™ Ultra 200S and 200HX Series Processors IOE-P I/O Registers

Bit Range	Default	Access	Field Name and Description
31:14	0h	RW	BAR (BASEADDR) Software programs this register with the base address of the device's memory region
13:4	0h	RO	Size Indicator (SIZEINDICATOR) Hardwired to 0 to indicate 16384 bytes of memory space
3	0h	RO	Prefetchable (PREFETCHABLE) A device can mark a range as prefetchable if there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables. Hardwired to 0 to indicate the device's memory space as notprefetchable.
2:1	2h	RO	Type (TYPE) Hardwired to 10 to indicate that Base register is 64 bits wide and mapping can be done anywhere in the 64-bit Memory Space.
0	0h	RO	Memory Space Indicator (MESSAGE_SPACE) Hardwired to 0 to identify a Memory BAR.

CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) BAR HIGH (BAR_HIGH)