Command Register (CMD) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Command Register (CMD) – Offset 4

This register provides coarse control over a devices ability to generate and respond to PCI cycles.

Bit Range	Default	Access	Field Name and Description
15:11	0h	RO	Reserved (RSVD0) This is a Reserved Register
10	0h	RW	Interrupt Disable (ID) Enables the device to assert an INTx#. When set, the Intel HD Audio subsystems INTx# signal will be de-asserted. When cleared, the INTx# signal may be asserted. Note that this bit does not affect the generation of MSIs.
9	0h	RO	Fast Back to Back Enable (FBE) Not implemented. Hardwired to 0.
8	0h	RW	SERR Enable (SEN) As a PCI device, this bit is an enable bit for the SERR# driver.
7	0h	RO	Wait Cycle Control (WCC) Not implemented. Hardwired to 0.
6	0h	RW	Parity Error Response (PER) As a PCI device, this bit controls the devices response to parity errors.
5	0h	RO	VGA Palette Snoop (VPS) Not implemented. Hardwired to 0.
4	0h	RO	Memory Write and Invalidate Enable (MWI) Not implemented. Hardwired to 0.
3	0h	RO	Special Cycle Enable (SCE) Not implemented. Hardwired to 0.
2	0h	RW	Bus Master Enable (BME) Controls standard PCI bus mastering capabilities for Memory and IO, reads and writes. Note that this also controls MSI generation since MSI are essentially Memory writes. 1 = Enable 0 = Disable.
1	0h	RW	Memory Space Enable (MSE) When set, enables memory space accesses to the Intel HD Audio subsystem.
0	0h	RO	I/O Space (IOS) The controller does not implement IO Space, therefore this bit is hardwired to 0.

Status Register (STS)

Device Identification (DID) Status Register (STS)