D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
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GPIO Commumity 5
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Integrated Sensor Hub (ISH) PCI Configuration
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- AHCI Index Register (INDEX)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
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SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0

D0idle_Max_Power_On_Latency register set at boot and Power control enable register to enable communication with the PGCB block below the Bridge

Bit Range	Default	Access	Field Name and Description
31:22	0h	RO	Reserved Field (RESERVED0) This Field Is Reserved
21	0h	RW/P	Hae Field (HAE) Hardware Autonomous Enable: If 1, then hardware may request power gating whenever it has reached an idle condition.
20	0h	RO	Reserved Field (RESERVED1) This Field Is Reserved
19	0h	RW/P	Sleep Enable Field (SLEEP_EN) SE: Sleep Enable: 1 = The function may assert Sleep during power gating. 0 =The function will never asset Sleep to the retention flops Note that some platforms may default this bit to 0, others to 1.
18	0h	RW/P	D3 Hen Field (D3HEN) If 1, then function will power gate when idle and the PMCSR [1:0] register in the function = b11 (D3).
17	0h	RW/P	Device Idle En Field (DEVIDLEN) If 1, then the function will power gate when idle and the DevIdle register (DevIdleC [2] = 1) is set.
16	0h	RW/P	Pmc Request Enable Field (PMCRE) If this bit is set to 1, the function will power gate when idle and PMC SW PG Req = 0.
15:13	0h	RO	Reserved Field (RESERVED2) This Field Is Reserved
12:10	2h	RW/O/P	Power Latency Scale Field (POW_LAT_SCALE) Power On Latency Scale
9:0	0h	RW/O/P	Power Latency Value Field (POW_LAT_VALUE) Power On Latency value

General Purpose Read Write Register1 (GEN_PCI_REGRW1)

Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) General Purpose Read Write Register1 (GEN_PCI_REGRW1)