Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) – Offset abe - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) – Offset abe

This is the Physical Layer 16.0 GT/s Lane 23 Equalization Control Register registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
15:12	fh	RW	Upstream Port 16 GT/s Port Lane 3 Transmitter Preset (UP16L3TP) Field contains the Transmit Preset value sent or received during Port 16 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \| A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
11:8	fh	RW	Downstream Port 16 GT/s Lane 3 Transmitter Preset (DP16L3TP) Transmitter Preset used for 16 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.
7:4	fh	RW	Upstream Port 16 GT/s Port Lane 2 Transmitter Preset (UP16L2TP) Field contains the Transmit Preset value sent or received during Port 16 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \| A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
3:0	fh	RW	Downstream Port 16 GT/s Lane 2 Transmitter Preset (DP16L2TP) Transmitter Preset used for 16 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.

Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)

Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)