Shadow Receive Buffer Register and Shadow Transmit Holding Register 0 (SRBR_STHR0) – Offset 30 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Shadow Receive Buffer Register and Shadow Transmit Holding Register 0 (SRBR_STHR0) – Offset 30

Bit Range	Default	Access	Field Name and Description
31:8	0h	NA	Reserved (Reserved0) Reserved
7:0	0h	RW	srbr_sthr0 (srbr_sthr0) This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. Reset Value: 0x0

Bit Range

Default

Access

Field Name and Description

31:8

Reserved (Reserved0)

Reserved

7:0

srbr_sthr0 (srbr_sthr0)

This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.
If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error.
If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs.
Reset Value: 0x0

Shadow Receive Buffer Register and Shadow Transmit Holding Register 1 (SRBR_STHR1)

Scratchpad Register (SCR) Shadow Receive Buffer Register and Shadow Transmit Holding Register 1 (SRBR_STHR1)