Memory Microcontroller Firmware Image (Type 5) Rules

1. The Memory Microcontroller (MMC) firmware image (Type 5) entry in the FIT is applicable to specific platforms, such as some server Xeon platforms. Please check your specific platform for applicability.
2. The FIT table may contain more than one Type 5 entry. The IFWI may carry multiple MMC images for multiple processors and steppings. Each Type 5 entry points to a distinct MMC FW image. The address field in Type 5 entry points to the first byte of the MMC FW image.
3. Each Type 5 entry must point to an address that is accessible by the processor at reset (i.e., requires no chipset configuration to reach that address in the flash).
4. The IFWI may have some empty Type 5 slots. These slots are set aside to store future MMC FW images. It is suitable for a Type 5 entry to point to these empty slots if the first dword in the empty slot is 0xFFFF_​FFFF.
5. MMC FW images pointed to by a type 5 entry must be aligned on a 16-byte address.
6. The IFWI stitching and construction process must not perform any additional compression, encoding, or encryption on the MMC FW image beyond what was already present in the delivered MMC FW image.
7. The C_​V bit in this entry should be clear to 0.
8. The Size field is not used. This field should be cleared to 0.
9. The version field is not used. This field should be cleared to 0.