| EMR1 | No Fix | No Fix | IPSR May Not Function Correctly |
| EMR2 | No Fix | No Fix | Poison Data Reported Instead of a CS Limit Violation |
| EMR3 | No Fix | No Fix | Monitor Instructions to Legacy VGA Region May Fail |
| EMR4 | No Fix | No Fix | TILEDATA State May Be Saved Incorrectly |
| EMR5 | No Fix | No Fix | A Poison Data Event May Not be Serviced if a Data Breakpoint Occurs on an AMX Tile-Load or AVX Gather or REP MOVS Instruction |
| EMR6 | No Fix | No Fix | IFS MSRs Will Ignore a Non-Zero EDX Value And Not Signal a #GP |
| EMR7 | No Fix | No Fix | Processor May Signal Spurious #GP Fault |
| EMR8 | No Fix | No Fix | A Break Point May be Hit Twice When a VM Exit Without Commit Occurs |
| EMR9 | No Fix | No Fix | Faulted XRSTORS Instruction May Result in Unexpected X87 FTW Value |
| EMR10 | No Fix | No Fix | Error Conditions Detected During Cold Reset May Not be Cleared by Subsequent Warm Reset |
| EMR11 | No Fix | No Fix | DSA/IAX Does Not Log The E2E Prefix Bit And The Prefix-Type Bits in AERTLPPLOG1 |
| EMR12 | No Fix | No Fix | The Processor May Drop Noncompliant Posted Peer-to-peer Transactions |
| EMR13 | No Fix | No Fix | Certain Bits in IA32_MC5_STATUS Register Will Always Return 0 |
| EMR14 | No Fix | No Fix | Occupancy Interrupt Handle is Not Checked Against Interrupt Table Size |
| EMR15 | No Fix | No Fix | Processor May Incorrectly Set PFD Assisted in Correction Bit in Memory Controller |
| EMR16 | No Fix | No Fix | DSA CMDSTATUS Register May Not Reflect Correct Hardware Status |
| EMR17 | No Fix | No Fix | Remapping Hardware May Set Access/Dirty Bits in a First-stage Page-table Entry |
| EMR18 | No Fix | No Fix | System Software May Not Receive VT-d Fault SPT.3 For Non-Zero Writes to b[191:HAW+128] |
| EMR19 | No Fix | No Fix | APCTL.APNGE Should be RW Instead of RWS |
| EMR20 | No Fix | No Fix | CXL Device May Not Receive Viral |
| EMR21 | No Fix | No Fix | Removed |
| EMR22 | No Fix | No Fix | Performance Monitoring Event Coherent_ops May Undercount |
| EMR23 | No Fix | No Fix | PCIe Link Re-Equalization May Not Occur if Link is in L1 State |
| EMR24 | No Fix | No Fix | Machine Check Bank 4 UCNA Errors May Not be Signaled |
| EMR25 | No Fix | No Fix | DSA/IAA Use of Priv and PASID |
| EMR26 | No Fix | No Fix | Reserved(0) Check For a PASID Table Entry May Not Happen For a DMA Request |
| EMR27 | No Fix | No Fix | Remapping Hardware May Not Generate a Page Request Group Response Message While Operating in Legacy Mode or Abort DMA Mode |
| EMR28 | No Fix | No Fix | Remapping Hardware May Abort ZLR to Second-Stage Write Only Pages |
| EMR29 | No Fix | No Fix | Remapping Hardware with Major Version Number 6 Incorrectly Advertises the ESRTPS Support |
| EMR30 | No Fix | No Fix | Platform May Hang if System Software Sends a Page Group Response or DevTLB Invalidation to Non-existent Requester ID |
| EMR31 | No Fix | No Fix | Remapping Hardware Does Not Perform Reserved (0) Check in Page Response Descriptor |
| EMR32 | No Fix | No Fix | Remapping Hardware Implements b[31:16] of the three Event Data Registers (VTDBAR offsets 0x3C, 0xA4, and 0xE4) as Read-Writable |
| EMR33 | No Fix | No Fix | IAA Do Not Report Overlap Errors For AECS Size of 2GB or Greater |
| EMR34 | No Fix | No Fix | DSA/IAA Invalid TC Not Reported in The SWERROR Register |
| EMR35 | No Fix | No Fix | IAA Unaligned Completion Record Address Error is Not Reported in SWERROR Register |
| EMR36 | No Fix | No Fix | Intel® UPI Link Not Resetting When L1 Mismatch Occurs Between Local and Remote Sockets |
| EMR37 | No Fix | No Fix | DSA/IAA May Fail to Log an MDPE Error For Back-to-Back Parity Errors |
| EMR38 | No Fix | No Fix | Relaxed Ordering Not Disabled by DEVCTL.ERO bit for DSA/IAA Upstream Transactions |
| EMR39 | No Fix | No Fix | System Address Logged For WDB Parity Errors May be Incorrect |
| EMR40 | No Fix | No Fix | Incorrect MCACOD For L2 MCE |
| EMR41 | No Fix | No Fix | System May Hang Due to Full LLRB |
| EMR42 | No Fix | No Fix | IAA May Fail to Properly Decode Data With a Large Header |
| EMR43 | No Fix | No Fix | Memory Controller Violates JEDEC RCD tCSALT Timing |
| EMR44 | No Fix | No Fix | Address May Not be Logged For a UCR Error Detected in The MLC |
| EMR45 | No Fix | No Fix | VT-d DMA Remapping Hardware May Hang if it Encounters Page Request Queue Overflow Condition |
| EMR46 | No Fix | No Fix | Receiver Common Mode Input Impedance May be Below Specification When Interface is Powered Down |
| EMR47 | No Fix | No Fix | Remapping Hardware Will Not Report The PASID Value For RTA.2 Faults in Modes Other Than Scalable Mode |
| EMR48 | No Fix | No Fix | Remapping Hardware Does Not Perform a Reserved(0) Check in Interrupt Remap Table Entry |
| EMR49 | No Fix | No Fix | Processor PCIe Root Port Link Spurious Data Parity Error May be Reported |
| EMR50 | No Fix | No Fix | Mismatch Between UboxErrMisc and MCI_STATUS Registers Error Logs |
| EMR51 | No Fix | No Fix | CHA UCNA Errors May be Incorrectly Controlled by MCi_CTL Enable Bits |
| EMR52 | No Fix | No Fix | Reading The PPERF MSR May Not Return Correct Values |
| EMR53 | No Fix | No Fix | No #GP Will be Signaled When Setting MSR_MISC_PWR_MGMT.ENABLE_SDC if MSR_MISC_PWR_MGMT.LOCK is Set |
| EMR54 | No Fix | No Fix | System May Experience an Internal Timeout Error When an Internal Parity Error Occurs While Working With Intel® AMX |
| EMR55 | No Fix | No Fix | Last Branch Records May Not Survive Warm Reset |
| EMR56 | No Fix | No Fix | Single Step on Branches Might be Missed When VMM Enables Notification On VM Exit |
| EMR57 | No Fix | No Fix | Incorrect #CP Error Code on UIRET |
| EMR58 | No Fix | No Fix | #GP May be Serviced Before an Instruction Breakpoint |
| EMR59 | No Fix | No Fix | Unexpected #PF Exception Might Be Serviced Before a #GP Exception |
| EMR60 | No Fix | No Fix | VMX-Preemption Timer May Not Work if Configured With a Value of 1 |
| EMR61 | No Fix | No Fix | User Interrupt Might be Delayed |
| EMR62 | No Fix | No Fix | VM Exit Qualification May Not be Correctly Set on APIC Access While Serving a User Interrupt |
| EMR63 | No Fix | No Fix | Software Tuning That Relies on PCLS Values May Experience Inaccurate Event Counts |
| EMR64 | No Fix | No Fix | Multiple SGX_Doorbell_Errors on Ubox Response Mismatch |
| EMR65 | No Fix | No Fix | Intel DSA/IAA Completion Record is Not Written For Non-Completion Record Invalid Traffic Classes |
| EMR66 | No Fix | No Fix | Intel IAA Expand Operation With PRLE Format Input May Return an Error |
| EMR67 | No Fix | No Fix | Intel IAA Compression with Compress Bit Order Set May Produce an Odd Number of Bytes |
| EMR68 | No Fix | No Fix | Intel IAA Source 2 Not Written Properly When Source 2 Size is 32 Bytes |
| EMR69 | No Fix | No Fix | Intel IAA May Not Report Invalid Filter Flags Status Code When Source 2 Bit Order Field is Set |
| EMR70 | No Fix | No Fix | Intel IAA Does Not Allow Source 1 Size to be 0 For Expand Operation |
| EMR71 | No Fix | No Fix | Intel® DSA/IAA And WQ Configuration Registers May be Incorrectly Updated |
| EMR72 | No Fix | No Fix | Invalid Flags Field of The Completion Record May Not be Set Correctly For Intel IAA Compression Operation |
| EMR73 | No Fix | No Fix | With Intel® SGX Disabled, Software That Relies on ENCLVexiting May Not Function as Expected |
| EMR74 | No Fix | No Fix | Headers Logged in AERHDRLOG for an AER Error for Intel DSA/IAA may be Incorrect |
| EMR75 | No Fix | No Fix | Intel DSA/IAA May Fail to Send an ERR_FATAL Message if a Non-Fatal Error Occurs in The Same Cycle |
| EMR76 | No Fix | No Fix | Intel DSA/IAA May Fail to Log an Unexpected Completion Error For an Invalid ATS Response |
| EMR77 | No Fix | No Fix | Intel IAA Compression Output Buffer Overflow Error May be Incorrectly Reported |
| EMR78 | No Fix | No Fix | Intel® QuickAssist Technology Accelerator May Violate ATS Invalidation Completion Ordering |
| EMR79 | No Fix | No Fix | Intel® QuickAssist Technology Accelerator Device May Not Invalidate PASID SupervisorPrivilege Translations Privilege Translations |
| EMR80 | Fixed | Fixed | The Time-Stamp Counter May Report an Incorrect Value |
| EMR81 | No Fix | No Fix | UPI Machine Check Bank May Not Report The Most Recently Logged Error |
| EMR82 | No Fix | No Fix | PECI Wire Host may Continuously Receive a Completion Code of 0x80 |
| EMR83 | No Fix | No Fix | DDR5 9x4 DIMMs ECS Data May be Reported Incorrectly |
| EMR84 | No Fix | No Fix | RETRY_RD_ERR_LOG_MISC.DDR5_9x4_half_device Bit Maybe Incorrect |
| EMR85 | No Fix | No Fix | PIROM Reports The Wrong 2 DPC Speed For Processors With Less Than 4800 MT/s 1 DPC Speed |
| EMR86 | No Fix | No Fix | An MDF Parity Error May Incorrect Set The Overflow Bit |
| EMR87 | No Fix | No Fix | Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed |
| EMR88 | No Fix | No Fix | CPUID Reports Incorrect Number of Ways For The Load DTLB |
| EMR89 | No Fix | No Fix | Intel PT Trace May Contain Incorrect Data When Configured With Single Range Output Larger Than 4KB |
| EMR90 | No Fix | No Fix | On Instructions Longer Than 15 Bytes, #GP Exception is Prioritized And Delivered Over #CP Exception |
| EMR91 | No Fix | No Fix | Mismatch on DR6 Value When Breakpoint Match is on Bitmap Address |
| EMR92 | No Fix | No Fix | RTM Abort Status May be Incorrect For INT1/INT3 Instructions |
| EMR93 | No Fix | No Fix | WRMSR to Reserved Bits of IA32_L3_QOS_Mask_15 Will Not signal a #GP |
| EMR94 | No Fix | No Fix | x87 FDP Value May be Saved Incorrectly |
| EMR95 | No Fix | No Fix | Debug Exceptions May Be Lost or Misreported When MOV SS or POP SS Instruction is Not Followed By a Write to SP |
| EMR96 | No Fix | No Fix | Exit Qualification For EPT Violations on Instruction Fetches May Incorrectly Indicate That The Guest-physical Address Was Writeable |
| EMR97 | No Fix | No Fix | Processor May Generate Spurious Page Faults On Shadow Stack Pages |
| EMR98 | No Fix | No Fix | Processor May Hang if Warm Reset Triggers During BIOS Initialization |
| EMR99 | No Fix | No Fix | IA32_MC1_STATUS MSR May Not Log Errors When IA32_MC1_CTL MSR is Set to Not Signal Errors |
| EMR100 | No Fix | No Fix | System May Hang When Bus-Lock Detection Is Enabled And EPT Resides in Uncacheable Memory |
| EMR101 | No Fix | No Fix | OFFCORE_REQUESTS_OUTSTANDING Performance Monitoring Events May be Inaccurate |
| EMR102 | No Fix | No Fix | Incorrect MCACOD For L2 Prefetch MCE |
| EMR103 | No Fix | No Fix | Call Instruction Wrapping Around The 32-bit Address Boundary May Return to Incorrect Address |
| EMR104 | No Fix | No Fix | ADDDC Reverse Sparing May Lead to Incorrect Data |
| EMR105 | No Fix | No Fix | SGX ENCLU[EACCEPT] Will Not Cause #GP When TCS.PREVSPP is Non-zero |
| EMR106 | No Fix | No Fix | Setting MISC_FEATURE_CONTROL.DISABLE_THREE_STRIKE_CNT Does Not Prevent The Three-strike Counter From Incrementing |
| EMR107 | No Fix | No Fix | Mismatch Between UboxErrMisc and MCI_STATUS Registers Error Logs |
| EMR108 | No Fix | No Fix | SST-TF May Fail to Report an Error if Turbo is Disabled |
| EMR109 | No Fix | No Fix | Unexpected Rollover in MBM Counters |
| EMR110 | No Fix | No Fix | System Crash Observed on Host When TD Private Pages Are Not Zeroed Out if Reused For Non-TD SW |
| EMR111 | No Fix | No Fix | IA32_MC2_ADDR And IA32_MC2_MISC MSRs Will be Cleared on Warm Reset |
| EMR112 | No Fix | No Fix | Multiple Write CRC Errors May Lead to System Hang |
| EMR113 | No Fix | No Fix | Intel DSA/IAA CTO Errors May Inconsistently Update the Prefix Log and Prefix Log Present Flag |
| EMR114 | No Fix | No Fix | RTIT_CTL.TRACE_EN May be Disabled at BIOS_DONE Even if it Was Previously Enabled |
| EMR115 | No Fix | No Fix | WRMSR to a Few Core MSRs Might be Overwritten |
| EMR116 | No Fix | No Fix | Performance Monitoring Events used by TMA May be Inaccurate |
| EMR117 | No Fix | No Fix | Performance Monitoring Event IDQ.MS_UOPS May Undercount |
| EMR118 | No Fix | No Fix | Scan At Field Scan Time Interval Violation Warning May be Reported Incorrectly |
| EMR119 | No Fix | No Fix | ECS Reads May Fail to Complete in Certain Memory Configurations and Conditions |
| EMR120 | No Fix | No Fix | A Write to The TSC_Deadline MSR May Cause an Unexpected Timer Interrupt |
| EMR121 | No Fix | No Fix | MSR_UNC_CBO_CONFIG Register May Not Provide Correct Information |
| EMR122 | No Fix | No Fix | Disabling The APIC While an Interrupt is Being Delivered May Cause a System Hang |
| EMR123 | No Fix | No Fix | DSA or IAA May Cause Unpredictable System Behavior When Incorrectly Forwarded Data |
| EMR124 | No Fix | No Fix | Unexpected System Software Behavior on Systems With Intel® Hyper-Threading Technology Enabled |
| EMR125 | | | Moved to EMRLCC1 |
| EMR126 | No Fix | No Fix | PCIe Link Degradation Following a Leaky Bucket Event |
| EMR127 | No Fix | No Fix | RTTO May Occur at Lower Link Speed And Reduce Link Width |
| EMR128 | No Fix | No Fix | Intel® DSA DIF Insert and DIF Strip Operations Do Not Properly Check For Overlapping Buffers |
| EMR129 | No Fix | No Fix | Remapping Hardware May Encounter Incorrect Error Code in Invalidation Queue Error Record Register |
| EMR130 | No Fix | No Fix | Intel DSA Memory Write with Incorrect Parity May Result in a System Crash |
| EMR131 | No Fix | No Fix | MCA not Logged for WbNoInvd Data ECC Errors |
| EMR132 | No Fix | No Fix | WRMSR Instruction to MSR_CORE_BIST MSR May Overwrite AMX State on Both Threads |
| EMR133 | Fixed | Fixed | Internal Timeout MCE May Occur on Systems with CXL I/O Devices |
| EMR134 | Planned Fix | Planned Fix | A PCIe Device May Not Function After a Warm Reset |
| EMR135 | No Fix | No Fix | DIMMs May Not be Placed in Self-Refresh Mode Prior to Warm Reset |
| EMR136 | Fixed | Fixed | Intel® DSA Device May Hang |
| EMR137 | Fixed | Fixed | VM Exit Following MOV to CR8 Instruction May Lead to Unexpected IDT Vectoring-Information |
| EMR138 | No Fix | No Fix | Power May Be Displayed Incorrectly |
| EMR139 | No Fix | No Fix | Processor May Hang When AMX_OPS_RETIRED PMON Event is Counted |
| EMR140 | Fixed | Fixed | Internal Timer Machine Check Error May Cause System Hang |
| EMR141 | No Fix | No Fix | PCIe TLP May be Lost After Link Down Event |
| EMR142 | Fixed | Fixed | Processor Core May Fail to Transition From C0 to C6 C-State |
| EMR143 | Fixed | Fixed | CPUID Returns Invalid Level Type |
| EMR144 | No Fix | No Fix | Write to UNCORE_RATIO_LIMIT May Not Take Effect |
| EMR145 | Fixed | Fixed | Memory Uncorrectable Error With Multiple Ranks on a Channel |
| EMR146 | Fixed | Fixed | A Processor May Run at a Fixed Mesh Frequency |
| EMR147 | Fixed | Fixed | REP SCASB or REP CMPSB Instructions May Return Incorrect Results |
| EMR148 | No Fix | No Fix | Incorrect Last Branch From Value in BTS Branch Record During a Task Switch |
| EMR149 | No Fix | No Fix | Intel® PT Incorrect CR3-Filtering |
| EMR150 | No Fix | No Fix | Intel® SST-PP Limited to Config-TDP Level 0 When PPL1 and PPL2 Are Not Set |
| EMR151 | No Fix | No Fix | Performance Monitoring Event MEMORY_ACTIVITY.STALLS_L2_MISS May Undercount |
| EMR152 | No Fix | No Fix | Certain VMCS Fields May be Incorrect During STM to VMX Transitions |
| EMR153 | No Fix | No Fix | Instruction Timeout VM Exit Will Not Set Guest RFLAGS.RF During #UD |
| EMR154 | No Fix | No Fix | VMREAD/VMWRITE Instructions May Not Fail When Accessing an Unsupported Field in VMCS |
| EMR155 | Fixed | Fixed | MPX_FUSE_OVERRIDE Register May Trigger General Protection Fault |