Interrupts

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Introduction
PCH Controller Device IDs
- Device and Revision ID
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
System Management
- Theory of Operation
  - Handling an Intruder
  - TCO Modes
High Precision Event Timer (HPET)
- Feature Overview
PCH Thermal Sensor
Power Delivery
- Power and Ground Signals
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
- Timer Programming
- Reading from the Interval Timer
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
- Signal Description
- Functional Description
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
- ICC
  - Signal Description
- I/O Signal Pin States
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
- Signal Description
- I/O Signal Planes and States

UART interface has an interrupt line which is used to notify the driver that service is required.

When an interrupt occurs, the device driver needs to read both the host controller and DMA status and TX completion interrupt registers to identify the interrupt source. Clearing the interrupt is done with the corresponding interrupt register in the host controller or DMA.

All interrupts are active high and their behavior is level interrupt.

Error Handling

Power Management Error Handling