600 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
Signal Description
Signal Name | Type | Description |
---|---|---|
GPIO fixed functions (Signals for Integrated Connectivity (CNVi) and Discrete Connectivity (CNVd) functions | ||
GPP_D5 / CNV_RF_RESET# | I/O | For CNVi: RF companion (CRF) reset signal, active low. Require a 75 kohm Pull-Down on platform/motherboard level. It is recommended not to use it for bootstrapping during early Platform init flows. For discrete connectivity with UART host support: Optional Bluetooth* I2S bus sync |
GPP_J2 / CNV_BRI_DT / UART0_RTS# | O | For CNVi: BRI bus TX. For discrete connectivity with UART host support: Bluetooth* UART RTS# |
GPP_J3 / CNV_BRI_RSP / UART0_RXD | I | For CNVi: BRI bus RX. For discrete connectivity with UART host support: Bluetooth* UART RXD |
GPP_J4 / CNV_RGI_DT / UART0_TXD | O | For CNVi: RGI bus TX. RGI_DT is used by the platform to strap presence of the CRF. Requires weak pull up of 20Kohm on the platform. For discrete connectivity with UART host support: Bluetooth* UART TXD |
GPP_J5 / CNV_RGI_RSP / UART0_CTS# | I | For CNVi: RGI bus RX. For discrete connectivity with UART host support: Bluetooth* UART CTS# |
GPP_J0 / CNV_PA_BLANKING | I/O | For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal. Used to be co-existence signal for external GNSS solution |
| I | For CNVi and discrete connectivity: Optional WLAN/Bluetooth* WWAN co-existence signal (Input) |
| O | For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal (Output) |
Fixed special purpose I/O | ||
CNV_WT_CLKP | O | CNVio bus TX CLK+ |
CNV_WT_CLKN | O | CNVio bus TX CLK- |
CNV_WT_D0P | O | CNVio bus Lane 0 TX+ |
CNV_WT_D0N | O | CNVio bus Lane 0 TX- |
CNV_WT_D1P | O | CNVio bus Lane 1 TX+ |
CNV_WT_D1N | O | CNVio bus Lane 1 TX- |
CNV_WR_CLKP | I | CNVio bus RX CLK+ |
CNV_WR_CLKN | I | CNVio bus RX CLK- |
CNV_WR_D0P | I | CNVio bus Lane 0 RX+ |
CNV_WR_D0N | I | CNVio bus Lane 0 RX- |
CNV_WR_D1P | I | CNVio bus Lane 1 RX+ |
CNV_WR_D1N | I | CNVio bus Lane 1 RX- |
Selectable special purpose I/O | ||
| I/O | Bluetooth* USB host bus (positive) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. |
| I/O | Bluetooth* USB host bus (negative) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. |
PCIE12_TXP | O | Wi-Fi* PCIe* host bus TX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function. |
PCIE12_TXN | O | Wi-Fi* PCIe* host bus TX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function. |
PCIE12_RXP | I | Wi-Fi* PCIe* host bus RX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function. |
PCIE12_RXN | I | Wi-Fi* PCIe* host bus RX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function. |
CLKOUT_PCIE_P3 | O | Wi-Fi* PCIe* host bus clock (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function. |
CLKOUT_PCIE_N3 | O | Wi-Fi* PCIe* host bus clock (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function. |
CL_RST# | O | Wi-Fi* CLINK host bus reset for discrete connectivity with CLINK support (Intel® vPro™). Optional to connect to a Wi-Fi* CLINK reset pin on the Intel® vPro™ Wi-Fi* module. |
CL_DATA | I/O | Wi-Fi* CLINK host bus data for discrete connectivity with CLINK support (Intel® vPro™). Optional to connect to a Wi-Fi* CLINK data pin on the Intel® vPro™ Wi-Fi* module. |
CL_CLK | O | Wi-Fi* CLINK host bus clock for discrete connectivity with CLINK support (Intel® vPro™). Optional to connect to a Wi-Fi* CLINK clock pin on the Intel® vPro™ Wi-Fi* module. |
W_Disable1# (GPIO) | O | Used for Wi-Fi* RF-Kill control. This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init). The signal must keep value in Sx state (configured in BIOS) The W_Disable signal have a Pull-up embedded in the CRF silicon, (this is an Active-Low signal). |
W_Disable2# (GPIO) | O | Used for Bluetooth* RF-Kill control. This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init). The signal must keep value in Sx state (configured in BIOS) The W_Disable signal have a Pull-up embedded in the CRF silicon, (this is an Active-Low signal). |