600 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
648364 | 05/10/2022 | Public |
Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
Signal Name | Type | Description |
---|---|---|
DMI0_TXP DMI0_TXN | O | DMI transmit lane 0 |
DMI0_RXP DMI0_RXN | I | DMI receive lane 0 |
DMI1_TXP DMI1_TXN | O | DMI transmit lane 1 |
DMI1_RXP DMI1_RXN | I | DMI receive lane 1 |
DMI2_TXP DMI2_TXN | O | DMI transmit lane 2 |
DMI2_RXP DMI2_RXN | I | DMI receive lane 2 |
DMI3_TXP DMI3_TXN | O | DMI transmit lane 3 |
DMI3_RXP DMI3_RXN | I | DMI receive lane 3 |
DMI4_TXP DMI4_TXN | O | DMI transmit lane 4 |
DMI4_RXP DMI4_RXN | I | DMI receive lane 4 |
DMI5_TXP DMI5_TXN | O | DMI transmit lane 5 |
DMI5_RXP DMI5_RXN | I | DMI receive lane 5 |
DMI6_TXP DMI6_TXN | O | DMI transmit lane 6 |
DMI6_RXP DMI6_RXN | I | DMI receive lane 6 |
DMI7_TXP DMI7_TXN | O | DMI transmit lane 7 |
DMI7_RXP DMI7_RXN | I | DMI receive lane 7 |